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sivaram
sivaram
Associate III
January 5, 2017
Question

Re synchronisation of 2 M24M02-DR eeproms

  • January 5, 2017
  • 1 reply
  • 1167 views

Posted on January 05, 2017 at 06:30

I am trying to implement Application note AN1471, There are two eeprom devices connected to the bus, First eeprom chip enable connected to gnd and the Second one to vcc(differentiated by device address). When i send the resyncronization logic on the bus. only the first eeprom recovers and the second doesn't recover till power cycle. The I2C bus failure was simulated by pulling the clock low in the middle of a I2C transfer.

So We changed the logic to connect the chip enable to microcontroller so that the controller pulls them high when required (keeping the device address same), In this case both of the eeprom doesn't recover from the unknown state till power cycle.

How to implement this if multiple eeprom's are connected to the same bus.

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1 reply

Seb
Seb
ST Employee
January 5, 2017
Posted on January 05, 2017 at 08:45

Some hints are available about I2C bus

https://community.st.com/0D50X00009XkW1mSAF

Regardless of a SW or HW I2C, a manual 9 STOP bit (no clock stretching) should do the job well.

Tip: If you'd like to have manyEEPROMs, 2 choices:

- Use GPIOs to control dynamically the chip enable (only one of them for exemple will be high level).

- No extra pins? Use an I2C IO Expander STMPE811 or else to control all the chip enables.

This technique is usually practiced on sensors running in a reliability oven, one MCU for 16 identical sensors.

Good luck!

sivaram
sivaramAuthor
Associate III
January 5, 2017
Posted on January 05, 2017 at 12:07

Hi 

We are already using GPIO to dynamically select the Chip enable. It is not working. 

Seb
Seb
ST Employee
January 5, 2017
Posted on January 05, 2017 at 13:04

Usually, before sending a START bit, the SDA and SCL lines should be checked for high levels.

If they are not, bus is in error condition. Recovery is to generate manually 9 STOP bits because if it is a glitch and data is hold low by slave(s), one of these STOP bit will go through and reset slaves. This series of 9 STOP bits should not check for clock stretch. The STOP bit could be continued until both SDA and SCL are high level, which is mandatory for START to occur.

If this technique is not possible, how about trying to use an MCU GPIO pin to supply voltage to EEPROMs and keep the enable different and static? GPIO max current seems compatible.

Beyond 2Mbit, SPI or QSPI memories seems more appropriate (higher bit rate) than I2C.

All the best!

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