Clock Security System (CSS)

Posted on May 17, 2011 at 10:19

Hello.

I want to use Safe oscillator function to control my oscillator state. It means i have to enable PLL. Enabling PLL gives Fclk=16MHz (ST7MC datasheet, page 23, figure 11) having 8MHz frequency at the input of PLL. According to same datasheet (page 32, figure 17) Fclk = 16 MHz gives at the output Fcpu = 8 MHz and Fmtc = 16 MHz(Normal mode, not slow mode).

1. Am i right?

2. Div2(page 23, figure 11) between oscillator and CSS is used only with 16MHz oscillator to get 8MHz frequency at the input of PLL, isn't it?

Tnx in advance

Posted on May 17, 2011 at 10:19

Ciao Luter,

I was out of office in the last period, so that's I am answering to just now.

For my side, what you wrote about CSS configurations, is right. Please, be sure to download the latest version of ST7MC datasheet for future references.

Regards,

Tanio