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harisuvarna
Associate III
April 7, 2025
Solved

STM32G4: USART buffer overrun during Flash Erase operation

  • April 7, 2025
  • 3 replies
  • 670 views

Hi ,

I am using STM32G4 to receive USART data from external interface and USART buffer overrun when USART interrupt conflicts with Flash Erase operation. 

As mentioned in STM32G4 Reference manual , in single bank mode, any read operation while writing/erasing flash 

stalls the bus until current flash operation is complete. To mitigate this performed following,

  • Moved ISR handler and subroutines invoked inside ISR to SRAM
  • Moved Interrupt Vector table to SRAM     

After all these changes , USART buffer still overruns when it conflicts with Flash erase operation

Request you to share your views.

Regards,

Hareesha

Best answer by harisuvarna

Hi All,

Thanks for the response . Issue is resolved now.

  • Moved, Interrupt table , all  ISR handler and associated functions into CCM SRAM memory location.
  • Moved functions invoked after flash erase start to CCM SRAM memory location.

Refer application notes section 2.2 to execute ISR handler from CCM SRAM.

https://www.st.com/resource/en/application_note/an4296-use-stm32f3stm32g4-ccm-sram-with-iar-embedded-workbench-keil-mdkarm-stmicroelectronics-stm32cubeide-and-other-gnubased-toolchains-stmicroelectronics.pdf

 

Regards,

Hareesha

 

3 replies

Karl Yamashita
Karl Yamashita
Principal
April 7, 2025

So there must be some command to have the STM32G4 to erase the flash. Do you not return and ack to let the external device start sending packets of data?

If a reply has proven helpful, click on Accept as Solution so that it'll show at top of the post.CAN Jammer an open source CAN bus hacking toolCANableV3 Open Source
H
harisuvarnaAuthor
Associate III
April 8, 2025

Hi ,

Thanks for the reply, Flash erase and write sequence works fine.  However  issue happens when Flash erase conflicts with USART data dequeuing. USART data reception is interrupt driven , data deque happens at UART ISR handler.

My understanding is Flash erase is interruptible. 

Regards,

Hareesha

Karl Yamashita
Karl Yamashita
Principal
April 8, 2025

Have you changed the interrupt priorities in the NVIC?

If a reply has proven helpful, click on Accept as Solution so that it'll show at top of the post.CAN Jammer an open source CAN bus hacking toolCANableV3 Open Source
H
harisuvarnaAuthor
Associate III
April 8, 2025

Also one more question, Can context switch happens when flash erase in progress?? CPU uses  AHB bus to perform Context switching.

Karl Yamashita
Karl Yamashita
Principal
April 8, 2025

Attach some code for the UART Callback and describe what you're doing to start the flash erase and the UART communication. And how much data are you receiving?

As @unknown mentioned, use the DMA in circular mode.

If a reply has proven helpful, click on Accept as Solution so that it'll show at top of the post.CAN Jammer an open source CAN bus hacking toolCANableV3 Open Source
H
harisuvarnaAuthorAnswer
Associate III
April 15, 2025

Hi All,

Thanks for the response . Issue is resolved now.

  • Moved, Interrupt table , all  ISR handler and associated functions into CCM SRAM memory location.
  • Moved functions invoked after flash erase start to CCM SRAM memory location.

Refer application notes section 2.2 to execute ISR handler from CCM SRAM.

https://www.st.com/resource/en/application_note/an4296-use-stm32f3stm32g4-ccm-sram-with-iar-embedded-workbench-keil-mdkarm-stmicroelectronics-stm32cubeide-and-other-gnubased-toolchains-stmicroelectronics.pdf

 

Regards,

Hareesha

 

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