How to get SWO working on STM32WB55

SWO seems to put the first few bytes into the TPIU fifo, and then the fifo goes to not ready and stays there.

I have the following init code for GPIOB-P3,

/* USER CODE BEGIN 2 */
/* configure Port B3 as SWO, this doesn't seem to get done by cube MX ? */
void SWO_GPIO_Init(void)
{
 GPIO_TypeDef *GPIOx = GPIOB;
 GPIO_InitTypeDef SWO_Init = {0};
 SWO_Init.Pin = GPIO_PIN_3;
 SWO_Init.Mode = GPIO_MODE_AF_PP;
 SWO_Init.Speed = GPIO_SPEED_FREQ_HIGH;
 SWO_Init.Pull = GPIO_NOPULL;
 SWO_Init.Alternate = GPIO_AF0_JTD_TRACE;
 HAL_GPIO_Init(GPIOx, &SWO_Init);
}
/* USER CODE END 2 */

and am trying to get SWO output at 57600 baud using this configuration.

static void SWO_Init(uint32_t portBits)
{
uint32_t SWOSpeed = 57600; // default 64k baud rate
uint32_t SWOPrescaler = (HAL_RCC_GetHCLK4Freq() / SWOSpeed) + 1; // SWOSpeed in Hz, //note that CPU_CORE_FREQUENCY_HZ is expected to be the AHB4 core clock
 
 CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; // enable trace in core debug
 TPI->SPPR = 0x00000002; // "Selected PIN Protocol Register": Select which protocol to use for trace output (2: SWO NRZ, 1: SWO Manchester encoding)
 TPI->ACPR = SWOPrescaler;//"Async Clock Prescaler Register". Scale the baud rate of the asynchronous output
 ITM->LAR = 0xC5ACCE55; // ITM Lock Access Register, C5ACCE55 enables more write access to Control Register 0xE00 :: 0xFFC
 ITM->TCR = ITM_TCR_TraceBusID_Msk | ITM_TCR_SWOENA_Msk | ITM_TCR_SYNCENA_Msk | ITM_TCR_ITMENA_Msk; // ITM Trace Control Register
 ITM->TPR = ITM_TPR_PRIVMASK_Msk; // ITM Trace Privilege Register
 ITM->TER = portBits; // ITM Trace Enable Register. Enabled tracing on stimulus ports. One bit per stimulus port.
 
 DWT->CTRL = 0x400003FE; // DWT_CTRL bits - meaning uncertain
 TPI->FFCR = 0x00000100; // Formatter and Flush Control Register - bit 1=0 => SWO output only
}

The SWO configuration has worked on other cortex M4 cores. Does anybody have an idea what might be missing? (separate clock for TPIU FIFO?)

Thanks