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Anton Chaban
Anton Chaban
Associate II
April 17, 2020
Solved

Huge repetitive LPTIM interrupts

  • April 17, 2020
  • 6 replies
  • 2372 views

I am trying to start with stm32wle5j but got stuck with LPTIM irq. I configure it but it always send me Interrupts. I need irq with period 2sec

I checked this post, but it didnt help me.

https://community.st.com/s/question/0D50X00009XkYEiSAN/huge-repetitive-lptim-interrupts

This is my code where i configure LPTIM

I setup RCC and enable LSE

 HAL_PWR_EnableBkUpAccess();
 
 __HAL_RCC_LSE_CONFIG(RCC_LSE_ON);
 
 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 ; // wait for it...
 
 __HAL_RCC_LPTIM1_CLK_ENABLE();
 __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE(); // enable clock to LPTIM peripheral also in low power mode
 __HAL_RCC_LPTIM1_FORCE_RESET();
 __HAL_RCC_LPTIM1_RELEASE_RESET(); // reset LPTIM interface
 __HAL_RCC_LPTIM1_CONFIG(RCC_CCIPR_LPTIM1SEL_0 | RCC_CCIPR_LPTIM1SEL_1);
 
 HAL_PWR_DisableBkUpAccess();

Then i configure LPTIM interrupts with period 2 sec

NVIC_SetPriority(LPTIM1_IRQn, 30);
 NVIC_EnableIRQ(LPTIM1_IRQn);
 // enable update (overflow) interrupt
 LPTIM1->IER = 0;
 
 LPTIM1->CR |= LPTIM_CR_ENABLE; // Enable LPTIM1
 LPTIM1->IER |= LPTIM_IER_ARRMIE; //Autoreload match Interrupt Enable
 LPTIM1->ARR = 0xffff; // set AutoReloadRegister 32768/65536 = 0.5 Hz
 LPTIM1->CR |= LPTIM_CR_CNTSTRT; // Start LPTIM

In LPTIM1_IRQHandler i check the isr and then i clear IRQ flags

void LPTIM1_IRQHandler(void)
{
 NVIC_ClearPendingIRQ(LPTIM1_IRQn);
 
 if (LPTIM1->ISR & LPTIM_ISR_ARRM)
 { // overflow
 
 }
 if ((LPTIM1->ISR & LPTIM_ISR_CMPM) && (LPTIM1->IER & LPTIM_IER_CMPMIE))
 { // expired
 
 }
 
 LPTIM1->ICR = LPTIM_ICR_CMPMCF | LPTIM_ICR_ARRMCF; // clear IRQ flags
}

But it isn't 2 sec period . It always interrupts my program and i can't reset it and.

I check that code in stm32L0xx and it works well. I see the different in LPTIM1 reg in WLE5 chip i have isr->ARROK and UE in 1 but in L0xx they in 0.

I attach LPTIM1 and RCC register value in files

This topic has been closed for replies.
Best answer by Anton Chaban

I finish my configuration LPTIM by LSE. I viewed wrongly __HAL_RCC_LSE_CONFIG . I use RCC_LSE_ON to configured LSE because it defined as RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON. But __HAL_RCC_LSE_CONFIG only check it, and set RCC_BDCR_LSEON only. I didnt check RCC register on RCC_BDCR_LSESYSEN set. RCC works well with LSE because RCC_BDCR_LSEON enough for it.

6 replies

waclawek.jan
waclawek.jan
Super User
April 18, 2020

Maybe you experience consequence of MCU may remain stuck in LPTIM interrupt when clearing event flag erratum?

You are clearing CMPM interrupt which is not enabled - try not doing that.

JW

Anton Chaban
Anton ChabanAuthor
Associate II
April 18, 2020

Thank you for your advice. But it didn't help me :(

To clear Irq added this code. 

 if(LPTIM1->ISR & LPTIM_ISR_CMPM)
 SET_BIT(LPTIM1->ICR, LPTIM_ICR_CMPMCF); // clear IRQ flags
 
 if(LPTIM1->ISR & LPTIM_ISR_ARRM)
 SET_BIT(LPTIM1->ICR, LPTIM_ICR_ARRMCF); // clear IRQ flags
 
 if(LPTIM1->ISR & LPTIM_ISR_UE)
 SET_BIT(LPTIM1->ICR, LPTIM_ICR_UECF); // clear IRQ flags

waclawek.jan
waclawek.jan
Super User
April 18, 2020

No, you are not supposed to clear a *disabled* interrupt, i.e. an interrupt, which does not have its corresponding bit in LPTIM_IER set.

Also, I don't know what's SET_BIT, but isn't it a Read-Modify-Write operation? You are not supposed to *read* LPTIMx_ICR, it's a write-only register.

JW

Anton Chaban
Anton ChabanAuthor
Associate II
April 22, 2020

My __HAL_RCC_LPTIM1_CONFIG code was wrong and i fixed it

RCC_CCIPR_LPTIM1SEL_0 | RCC_CCIPR_LPTIM1SEL_1 was for STM32L0xx series chips i changed it to RCC_LPTIM1CLKSOURCE_LSE

So RCC_LPTIM1SEL was 0x0 and with code RCC_LPTIM1CLKSOURCE_LSE it was changed to 0x3

but it's leaded to stuck in check ARROK flag 

 LPTIM1->IER = 0;
 LPTIM1->IER |= LPTIM_IER_ARRMIE; //Autoreload match Interrupt Enable
 LPTIM1->CFGR = 0;
 LPTIM1->CR |= LPTIM_CR_ENABLE; // Enable LPTIM1
 LPTIM1->ARR = 0xffff; // set AutoReloadRegister 32768/65536 = 0.5 Hz
 
 while((LPTIM1->ISR & LPTIM_ISR_ARROK) != LPTIM_ISR_ARROK);// <- stuck there!!!!
 
 LPTIM1->CR |= LPTIM_CR_CNTSTRT; // Start LPTIM

Also i tried to use HAL instead, but HAL_LPTIM_Init it returns HAL_TIMEOUT 

 hlptim.Instance = LPTIM1;
 hlptim.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
 hlptim.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1;
 hlptim.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;
 hlptim.Init.Trigger.ActiveEdge = LPTIM_ACTIVEEDGE_FALLING;
 hlptim.Init.Trigger.SampleTime = LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION;
 hlptim.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_LOW;
 hlptim.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE;
 hlptim.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL;
 hlptim.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO;
 hlptim.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO;
 hlptim.Init.RepetitionCounter = 0;
 
 lptim_setLptimIrqHandler(NULL, NULL);
 
 HAL_LPTIM_Init(&hlptim);

LPTIM1/LPTIM2/LPTIM3 Also doesn't work;

if i use LSI instead of LSE it works.

I check my LSE and it works. I was able to start up RTC with LSE.

Anton Chaban
Anton ChabanAuthor
Associate II
April 22, 2020

I was wrong RTC doesn't work with LSE. I forgot to reset BackUp Domen(bdrst) before setup LSE.

I copied this code from HAL and use it to clear irq flags. And its work Okey with LSI. Than you for advises and spent time. It seems like my oscillator's bad. But that is another story

if (__HAL_LPTIM_GET_FLAG(&gLPTimGlobals._hlptim, LPTIM_FLAG_ARROK) != RESET)
 {
 if (__HAL_LPTIM_GET_IT_SOURCE(&gLPTimGlobals._hlptim, LPTIM_IT_ARROK) != RESET)
 {
 /* Clear Autoreload write flag */
 __HAL_LPTIM_CLEAR_FLAG(&gLPTimGlobals._hlptim, LPTIM_FLAG_ARROK);
 }
 }
 

Remi QUINTIN
Remi QUINTIN
Technical Moderator
April 21, 2020

The value written in the LPTIM_ARR register is not 32768 (0x7FFF). So the overflow is triggered immediately and all the time as the CNTSTRT bit is set to 0 = continuous mode by default.

Anton Chaban
Anton ChabanAuthor
Associate II
April 21, 2020

32768  is a external oscillator's frequency and 65535 it's a max value of tick needed for Autoreload match Interrupt.

Remi QUINTIN
Remi QUINTIN
Technical Moderator
April 21, 2020

My mistake. My second sentence is false as the counter is reset.

Anton Chaban
Anton ChabanAuthorAnswer
Associate II
May 7, 2020

I finish my configuration LPTIM by LSE. I viewed wrongly __HAL_RCC_LSE_CONFIG . I use RCC_LSE_ON to configured LSE because it defined as RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON. But __HAL_RCC_LSE_CONFIG only check it, and set RCC_BDCR_LSEON only. I didnt check RCC register on RCC_BDCR_LSESYSEN set. RCC works well with LSE because RCC_BDCR_LSEON enough for it.

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