Entry point address = 0x84000000 (linuxkernel1) gives IAC 137 error due to SERC 32

Question

When U-boot is going to startup at the entry point address = 0x84000000, then this happens.

IAC ID 137 is RISAF4 - DDR-SDRAM.

SERC ID 32 is USART2.

I don't know why USART2 seems to write at the Optee address region (0x82000000 - 0x83FFFFFF) and it all lands on 0x83FFFF80. The optee address region is secure and USART2 seems to write on this address.

I have attached my complete device tree and I wonder if the ST dev team can help me to find why USART2 is trying to access 0x83FFFF80 in DDR-SDRAM?

My processor is STM32MP257FAK.

Note 1: The difference between 0x84000000 and 0x83FFFF80 is 128, e.g one byte. So I guess that something is shifted wrongly here?

Note 2: I'm using LDO2 as VDDIO_SDCARD and BUCK7 for 3v3 for VDD_SDCARD. Because my PMIC is the STPMIC25A and not STPMIC25D.

F/TC:0 0 pmic_get_voltage:192 vddgpu_pmic: get voltage: 800000 uV
D/TC:0 0 set_opp:67 set clock to 800000kHz
I/TC: Primary CPU switching to normal world boot
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x84000000
INFO: SPSR = 0x3c9
E/TC:0 stm32_serc_handle_ilac:133 SERC exceptions [63:32]: 0x1
E/TC:0 stm32_serc_handle_ilac:139 SERC exception ID: 32
E/TC:0 stm32_iac_itr:192 IAC exceptions [159:128]: 0x200
E/TC:0 stm32_iac_itr:197 IAC exception ID: 137
I/TC:

DUMPING DATA FOR risaf@420d0000
I/TC: =====================================================
I/TC: Status register (IAESR0): 0x91
I/TC: -----------------------------------------------------
I/TC: Faulty address (IADDR0): 0x83ffff80
I/TC: =====================================================
E/TC:0 Panic at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r3/core/drivers/firewall/stm32_iac.c:212 <stm32_iac_itr>
E/TC:0 TEE load address @ 0x82000000
E/TC:0 Call stack:
E/TC:0 0x82008180
E/TC:0 0x820473cc
E/TC:0 0x82030028
E/TC:0 0x82044d44
E/TC:0 0x82014bf8

Also, I'm using the USART6 as debug output. I don't know how exactly set the debug to USART6 in U-boot, but I guess I need to create a patch in Yocto for changing the stm32mp25_defconfig file?

Date: Thu, 7 May 2026 22:06:34 +0200
Subject: [PATCH] Add log console output for u-boot

---
 configs/stm32mp25_defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig
index 0c8359a94e..1374481db7 100644
--- a/configs/stm32mp25_defconfig
+++ b/configs/stm32mp25_defconfig
@@ -195,3 +195,8 @@ CONFIG_FWU_MULTI_BANK_UPDATE=y
 CONFIG_FWU_MDATA_V2=y
 # CONFIG_TOOLS_MKEFICAPSULE is not set
 # CONFIG_TOOLS_MKFWUMDATA is not set
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_STM32=y
+CONFIG_LOG=y
+CONFIG_LOG_MAX_LEVEL=7
+CONFIG_LOG_DEFAULT_LEVEL=7
-- 
2.43.0

And selecting the USART6 instead of USART2 for TF-A.

From: noname <noreply@example.com>
Date: Thu, 7 May 2026 19:44:45 +0200
Subject: [PATCH] Change USART2 to USART6 for early boot debug

---
 plat/st/stm32mp2/stm32mp2_def.h | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index a616e2fbf..e5e8ce1af 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -459,21 +459,21 @@ enum ddr_type {
 
 /* For UART crash console */
 #define STM32MP_DEBUG_USART_CLK_FRQ		64000000
-/* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */
-#define STM32MP_DEBUG_USART_BASE		USART2_BASE
-#define DEBUG_UART_TX_GPIO_BANK_ADDRESS		GPIOA_BASE
-#define DEBUG_UART_TX_GPIO_BANK_CLK_REG		RCC_GPIOACFGR
-#define DEBUG_UART_TX_GPIO_BANK_CLK_EN		RCC_GPIOxCFGR_GPIOxEN
-#define DEBUG_UART_TX_GPIO_PORT			4
-#define DEBUG_UART_TX_GPIO_ALTERNATE		6
-#define DEBUG_UART_TX_CLKSRC_REG		RCC_XBAR8CFGR
-#define DEBUG_UART_TX_CLKSRC			XBAR_SRC_HSI
-#define DEBUG_UART_TX_EN_REG			RCC_USART2CFGR
-#define DEBUG_UART_TX_EN			RCC_UARTxCFGR_UARTxEN
-#define DEBUG_UART_RST_REG			RCC_USART2CFGR
-#define DEBUG_UART_RST_BIT			RCC_UARTxCFGR_UARTxRST
-#define DEBUG_UART_PREDIV_CFGR			RCC_PREDIV8CFGR
-#define DEBUG_UART_FINDIV_CFGR			RCC_FINDIV8CFGR
+/* USART6 on HSI@64MHz, TX on PF13 Alternate 3 */
+#define STM32MP_DEBUG_USART_BASE USART6_BASE
+#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOF_BASE
+#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOFCFGR
+#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN
+#define DEBUG_UART_TX_GPIO_PORT 13
+#define DEBUG_UART_TX_GPIO_ALTERNATE 3
+#define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR
+#define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI
+#define DEBUG_UART_TX_EN_REG RCC_USART6CFGR
+#define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN
+#define DEBUG_UART_RST_REG RCC_USART6CFGR
+#define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST
+#define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR
+#define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR
 
 /*******************************************************************************
 * STM32MP2 IPCC
-- 
2.43.0

The correct and expected output should be something like this:

I/TC: Primary CPU switching to normal world boot
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x84000000
INFO: SPSR = 0x3c5
I/TC: Reserved shared memory is disabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are enabled


U-Boot 2023.10-stm32mp-r1 (Oct 02 2023 - 14:39:59 +0000)

CPU: STM32MP257FAK Rev.Y
Model: STMicroelectronics STM32MP257F-DK Discovery Board
Board: stm32mp2 (st,stm32mp257f-dk)
Board: MB1605 Var1.0 Rev.C-01
DRAM: 4 GiB
optee optee: OP-TEE: revision 4.0 (2a5b1d12)
I/TC: Reserved shared memory is disabled

I'm using OE manifest from ST: https://github.com/STMicroelectronics/oe-manifest

As you can see, I'm using the latest meta-st layer.

mint@mint-ThinkPad-W540:~/Documents/Github/Watermelon-Wine-1A/watermelon-wine-os/layers/meta-st/meta-st-stm32mp-addons$ git log --oneline -n 10
3597fb3 (HEAD, tag: openstlinux-6.6-yocto-scarthgap-mpu-v26.02.18, m/refs/tags/openstlinux-6.6-yocto-scarthgap-mpu-v26.02.18, OpenSTLinux/scarthgap) CUBEMX-STM32MP: configure use of CUBEMX_M33_TZ
c67adfc MACHINE: set m33fw default configuration
9322326 M33TDPROJECTS-STARTER-STM32MP2: set specific CubeMX configuration
9298ce1 MACHINE: enable external tf-m platform profile from CubeMX project
ca6f576 MACHINE: update for CubeMX tf-m platform source
8078626 MACHINE: update for m33fw configuration
9eb0628 M33TDPROJECTS-STARTER-STM32MP2: update folder name
6d5e442 MACHINE: force use of CUBEMX_DTB on extlinux.conf file
d6f276a M4PROJECTS-STM32MP1: update folder name
15be8c7 M33TDPROJECTS-STARTER-STM32MP2: fix missing inherit for CubeMX class
mint@mint-ThinkPad-W540:~/Documents/Github/Watermelon-Wine-1A/watermelon-wine-os/layers/meta-st/meta-st-stm32mp-addons$ cd ..
mint@mint-ThinkPad-W540:~/Documents/Github/Watermelon-Wine-1A/watermelon-wine-os/layers/meta-st$ cd meta-st-stm32mp
mint@mint-ThinkPad-W540:~/Documents/Github/Watermelon-Wine-1A/watermelon-wine-os/layers/meta-st/meta-st-stm32mp$ git log --oneline -n 10
e53460d (HEAD, tag: openstlinux-6.6-yocto-scarthgap-mpu-v26.02.18, m/refs/tags/openstlinux-6.6-yocto-scarthgap-mpu-v26.02.18) Update SBOM on EULA
6caba0f SDK-INFOS: fix typo and align examples
5007f7f CUBE MP2: 1.3.0
df3a656 EXTERNAL-DT: v6.0-stm32mp-r3
db192f8 KERNEL: v6.6-stm32mp-r3
ec7b429 TF-A: v2.10-stm32mp-r3
fb55b14 TF-M: v2.1.3-stm32mp-r2
2d48668 TF-M: v2.1.3-stm32mp-r2
1bfbbd0 U-BOOT: v2023.10-stm32mp-r3
cda5991 OPTEE: 4.0.0-stm32mp-r3
mint@mint-ThinkPad-W540:~/Documents/Github/Watermelon-Wine-1A/watermelon-wine-os/layers/meta-st/meta-st-stm32mp$ cd ..
mint@mint-ThinkPad-W540:~/Documents/Github/Watermelon-Wine-1A/watermelon-wine-os/layers/meta-st$ cd meta-st-openstlinux/
mint@mint-ThinkPad-W540:~/Documents/Github/Watermelon-Wine-1A/watermelon-wine-os/layers/meta-st/meta-st-openstlinux$ git log --oneline -n 10
993e43a (HEAD, tag: openstlinux-6.6-yocto-scarthgap-mpu-v26.02.18, m/refs/tags/openstlinux-6.6-yocto-scarthgap-mpu-v26.02.18, OpenSTLinux/scarthgap) OPTEE ADDONS: License, code of conduct
e21bbfb LICENSE management: manage splitted partitions
b58df11 DCMIPP ISP: histogram
4d95d93 EVENT GTK, WESTON CUBE: add code of conduct
cbe39f5 libcamera: 0.3.0 with ST IPA
66b4af2 PKGGROUP: add libcamera
2a3dd12 INITRD: load kernel module before resize
425bdc4 IMAGE: add M33TD splashscreen and service
c7ad3bd INITRD: use kmod instead of busybox kmod
d5228dc PKG OPTEE: cleanup
mint@mint-ThinkPad-W540:~/Documents/Github/Watermelon-Wine-1A/watermelon-wine-os/layers/meta-st/meta-st-openstlinux$

DMårt · Accepted Answer

This solved the issue:

https://community.st.com/t5/stm32-mpus-embedded-software-and/changing-default-debug-uart-on-stm32mp257f-ev1/td-p/810070

A change in the DT for u-boot.

See screenlog.0(5).txt

Also, it's important to sett the USART6 base address inside the stm32mp25_defconfig as well!

CONFIG_DEBUG_UART_BASE=0x40220000

Yes, I know that ST say that's only needed for STM32MP1, but it's important for STM32MP2 as well.

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