Could you please provide example device tree configuration for STM32MP157a MPU with Ethernet PHY without own quartz, so clock signal (50 MHz) must be generated by MPU. I tried to follow device tree documentation, but no success. Regards Arkadiusz

Hi Arkadiusz,

from your request of 50 MHz, I suppose to are using the PHY in RMII mode.

You need to follow the clock block diagram in the Reference Manual, chapter 10.4.8 "clock distribution for Ethernet (ETH)".

1) generate internally a clock 50 MHz

from the block diagram this has to be either at pll4_p or pll3_q.

At Linux kernel prompt you can type "cat /sys/kernel/debug/clk/clk_summary" to display the current clock tree and then decide which PLL to change.

This settings has to be done in the device tree of TF-A (if you use trusted boot) or of U-Boot (if you use basic boot). The two device tree are exactly the same, so no additional complexity whatever you decide to use.

In the default ST configuration pll4_p is 100MHz and already used by SD cards. Decreasing it at 50 MHz will impact boot time performance. Of course you can move the SD on another clock, but let's play easy in this example.

So let's use pll3_q and keep SD on the default!

In TF-A DT file in ./fdts/stm32mp1XXXX, you need to replace CLK_ETH_DISABLED with CLK_ETH_PLL3Q in the property st,pkcs of rcc.

In the same file you need to adapt the frequency of PLL3. This should work fine (I assume same crystal 24 MHz as default DT):

/* VCO = 400.0 MHz => P = 200, Q = 50, R = 12.5 */
pll3: st,pll@2 {
 cfg = < 2 49 1 7 31 PQR(1,1,1) >;
};

2) enable the gating and the pin to get clock out

from the block diagram, the control bit ETHCKEN must enable the gate. This is controlled by the kernel device tree for the ethernet:

  To clock-names add "eth-ck" and "syscfg-clk"

  To clocks add ETHCK_K and SYSCFG

Then in the pin-control for ethernet you have to set the pin for the proper function, e.g.

<STM32_PINMUX('G', 8, AF2)>, /* ETH_CLK */

All the info about pin multiplexing are in the datasheet. You need to create at least ethernet0_rmii_pins_a, but good to have also ethernet0_rmii_pins_sleep_a

At this point the clock should be already available at the output.

3) The same clock you send out has to be feed-back internally

This means setting the control bit ETH_REF_CLK_SEL.

This is also done in kernel device tree for the ethernet, by the boolean flag

st,eth_ref_clk_sel = <1>;

So, the kernel board DT for ethernet should be:

&ethernet0 {
 status = "okay";
 pinctrl-0 = <&ethernet0_rmii_pins_a>;
 pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
 pinctrl-names = "default", "sleep";
 st,eth_ref_clk_sel = <1>;
 clock-names = "stmmaceth",
 "mac-clk-tx",
 "mac-clk-rx",
 "eth-ck",
 "syscfg-clk",
 "ethstp";
 clocks = <&rcc ETHMAC>,
 <&rcc ETHTX>,
 <&rcc ETHRX>,
 <&rcc ETHCK_K>,
 <&rcc SYSCFG>,
 <&rcc ETHSTP>;
 phy-mode = "rmii";
 max-speed = <100>;
};