STM32F722 UART data error according to SYSCLK
Hi,
I use STM32F722 on a custom board for UART communication with an external sensor.
When using SYSCLK with the maximum clock of 216 MHz using HSI and PLL, UART data was lost 2~3 bytes when 250 bytes were transmitted at once during UART communication with an external sensor.
It was the same even if I changed the UART CLK.
However, when SYSCLK was set to 140 MHz or lower, data was not lost regardless of UART CLK.
I tried the same using the NUCLEO-F722ZE board to use the proven hardware.
When tested by adding UART in the CubeMX default setting (HSE, SYSCLK 216) of the NUCLEO-F722ZE board, No data was lost.
And when HSI was set to divide PLL, CLK error was displayed.
When I ignored the error and generated the code, the same phenomenon as the custom board occurred(No data loss occurs when SYSCLK is used below 140).
Q1. What causes CLK error when setting SYSCLK using HSI and PLL in NUCLEO-F22ZE?
Q2. What is the correlation between SYSCLK and UART data error?
Thank you.