Hi When I try to set DSI clock more than 500M, the STM32cubemx will display an error message "dsi clock source frequency must be =< 62MHz" as below. But it said STM32H747 DSI clcok can reach 1Ghz in datasheet.
I use 25Mhz HSE and attach STM32cubemx project for reference.
Because it's the data across multiple lanes that can get to 1 Gbps
2-Lanes, clocking at 500 MHz each, the DSI clock on the wire is 250 MHz, with data lanes clocking on BOTH edges
The 62 MHz is the pixel clock, for a 16 or 24-bit load, the LTDC delivers words to the DSI, the DSI moves it a bit/lane over the wire.
16 x 62 = 992 bps
I suspect 16 x 62.5 = 1000 bps is the functional limit, or close too it.
The 24-bit colour depth the maximum pixel clock is closer to 41.67 MHz
If you don't like the limits the auto-gen tools apply, stop using them, and use your interpretation of the reference manual and the peripheral mechanics.
>I suspect 16 x 62.5 = 1000 bps is the functional limit, or close too it.
-->I think it would be better if it was officially confirmed, so let's wait for ST's answer.
>If you don't like the limits the auto-gen tools apply, stop using them, and use your interpretation of the reference manual and the peripheral mechanics.
-->The cubemx can save many time when starting a new project, I am just confused with this limitation.
Position yourself so that you are not dependent on fast updates to CubeMX but rather are self-sufficient to ensure success. Look at the release schedule for the past few builds. Expect that it will take at least this much time.
"If you feel a post has answered your question, please click ""Accept as Solution""."