STM32 MCUs Security

Suppose I want to implement firmware for STM32U3 without TZ enabled and without the use of GTZC, then I could mostly use the MPU_NS and the TZ-Aware peripheral protection (EXTI, FLASH, RCC, PWR, GPDMA, SYSCFG, RTC & TAMP).   My goal is to limit unprivileged code execution to main FLASH, no SRAM, no OCTOSPI NOR/PSRAM.   The problem is now the ICACHE. Is there a way to force it to be privileged only ?   If not, assuming that I am allowing only unprivileged execution access via MPU_NS to the main FLASH (0x08000000 - (0x08000000 + size of flash)), could the remapping feature of the ICACHE be used to map say SRAM into this region and somehow unprivileged execution access this way ?   The docs are unclear there. The remap mechanism is described as a generic mechanism, not limited to any subset of the 0x00000000 - 0x1fffffff address space. Which means that in theory one could replace the mapping at 0x08000000 t

There is a problem with STM32 signing tool version 2.21.0. When header version is 2.3 and alignment flag is used, then image length in header is greater by the alignment byte count.To reproduce:Create dummy.bin that is filled with 256 bytes of FF's. For example with HxD tool.Sign it with no keys:STM32_SigningTool_CLI.exe -bin dummy.bin --type fsbl --no-keys --option-flags 0x80000000 --output signed.bin --dump-header signed.bin --header-version 2.3 --alignView the signed.bin with hex viewer (e.g. HxD) at offset 0x6C which is Image length by UM3234 rev 2:

I read UM3451 (STM32N6xx security guidance for SESIP level 3 certification) chapter 3.2.2 Secure installation and I wonder why aren't the FSBL signature public keys not written into OTP fuses? Only the 8 words (32 bytes) of hashes of all 8 public keys are written by the instructions.Chapter 2.1. Secure boot here in wiki explains that one of 8 active public key hashes in FSBL binary header is compared to the one in OTP and if they match, then "that" public key is trusted. But it doesn't explicitly say where does "that" public key come from.From UM3234 concept drawings (Figure 12-13.) I begin to understand that public key (in some changed form) is provided with the FSBL authentication extension header. So does it mean the MCU does not

We've been using STiROT + OEMuROT for STM32H7S on our system, with our own application.The secure bootloader handles most of its functionality very well, and the security aspects in particular. The scripts provided by ST were very helpful, as was the documentation on the ST wiki. We are grateful to ST for providing these.However, it proved extremely challenging to get the secure bootloader working with our application, mainly because the secure bootloader makes a number of important assumptions about the user application which are not documented.These unstated assumptions initially prevented our application from running, and it took a considerable amount of time and effort to solve all the problems associated with them.AssumptionsThe main assumptions are:OEMuROT assumes that the application will use the same clock setup as itself (especially PLL1 and PLL2): as documented i

I'm working on a custom STM32U5 board and I'm trying to harden the system.I followed the AN5347 (https://www.st.com/resource/en/application_note/an5347-arm-trustzone-features-for-stm32l5-and-stm32u5-series-stmicroelectronics.pdf) in particular I followed the chapter 10 with success as I was able to raise up to RDP=2 with OEM password and back to RDP=0.Then I tried for the second time using the STM32CubeProgrammer instead of the command line as described in the application note, but I got some issues at step 5: Set RDP level 2. The STM32CubeProgrammer did not end the process and got stuck writing RDP=0xCC in the option byte and after ten minutes I forced the termination of the GUI.After that I was not able to recover to RDP=0.Every time I try to send a

When creating a new project (for STM32H573) using CubeMX, it generates defaults keys under ROT_Provisioning\SM\Keys:06/19/2025 03:20 PM 232 ITS_key1.pem02/17/2026 09:34 PM 16 SFI_Encryption_Key.bin02/17/2026 09:34 PM 12 SFI_Encryption_Nonce.bin02/18/2026 12:06 PM 136 SFI_Global_License.bin06/19/2025 03:20 PM 246 SM_Authentication.pem06/19/2025 03:20 PM 182 SM_Authentication_pub.pem06/19/2025 03:20 PM 246 SM_Encryption.pem06/19/2025 03:20 PM 182 SM_Encryption_pub.pemUsing TPC, those keys (including the SFI_global_license) can be regenerated, but when provisioning, got the following error:2026-02-18 12:19:23,911 - DEBUG - Processing license...2026-02-18 12:19:24,072 - DEBUG - Error: Execution of RSS

I created a sample project using the STM32N657-DK, but when I try to debug using ST-LINK, each project does not work and results in a HardFault or similar error.I also tried loading them simultaneously from the debug configuration, but it was not successful.How can I properly debug both AppliSecure and AppliNonSecure? Also, is this the correct way to create a sample using the TrustZone feature of the STM32N6570-DK?I would appreciate your guidance.I am using STM32CubeIDE version 1.19.0.For the sample project I created, I made "FSBL", "AppliNonSecure", and "AppliSecure". 

We need the secure boot and secure firmware update solution for both the execution models to meet the EU-CRA standard:• Execute in place support (XiP support) - direct execute from external QSPI flash• BootROM support - copy from QSPI flash to SDRAM, and execute from SDRAM 

Hello ST Support,I reproduced an ETH TX DMA issue on STM32N6570-DK where the DMA never consumes the TX descriptor.Environment- Board: STM32N6570-DK- Security: TrustZone enabled, Secure-only platform configuration- PHY: ID1=0x001C, ID2=0xC916, link-up confirmed- Interface: RGMII, 1G linkObserved behavior- HAL_ETH_Transmit*() submit succeeds (st=0)- TX descriptor OWN bit remains 1 (never cleared by DMA)- TX complete callback/counter never increments- DMA enters/keeps TBU state- Key symptom: DMACCATXBR remains 0 (buffer base is never loaded)Representative logs- [eth][post-start] dlar=0x3402C1E0 dtpr=0x3402C1E0 rlr=0x00000003 txcr=0x00200001 dmacc=0x00080218 txqomr=0x0007000A- [tx][path] st=0 own=0->1 catxdr=0x3402C1E0->0x3402C1E0 catxbr=0x00000000->0x00000000 csr=0x00000000->0x00000004- [tx][stall] own=1 ... catxdr=0x3402C1E0 catxbr=0x00000000 csr=0x00000004 ... dmad=0x000

Have successfully worked throughSTM32Cube_FW_U5_V1.8.0/Projects/B-U585I-IOT02A/Applications/SBSFU/readme.htmlI need to port this (..boot, ..loader, ..appli) to a custom board running STM32U585VIT6.Within the readme it states "This example has been tested with STMicroelectronics B-U585I-IOT02A board and can be easily tailored to any other supported device and development board."Is there an example / idiots guide to work through doing the above?Thanks 

Hello,I'm developing an application with OEMiRoT and trustzone for STM32H563.I'm getting a write protection error (WRPERR) when I try to erase a secure flash sector from secure code that is not protected neither by write protection or HDP. I'm using the method HAL_FLASHEx_Erase() and I mapped the region as readable and writable with the memory management tool of CubeMX.If I try to do the same process without the secure boot provisioning, everything works as expected. I would like to know if there are any additional operation in order to write/erase flash at runtime when secure boot is used.Any help is really appreciated!Thank you,Giulio

I am looking for information that compares the security in an STM32U5 or similar with the PUF-based solutions used in competitor's processors.  The problem is that "PUF" has a simple explanation that sounds good and a head-to-head analysis of the advantage of these other processors against what ST provides seems to be lacking in the market place.  Obviously, ST could have selected a PUF-based security and decided not to do so, so the clues might exist in why that decision was reached.  Note:  The primary focus is to find processors that prevent software pirates from extracting the firmware.  Any help that addresses this will no doubt be repaid in future design wins.

Hello everyone,I’m working on a project with Secure Manager on STM32H573IIK3Q using the STM32H573-DK board. I have followed the official tutorial from ST to make my application compatible with Secure Manager:https://wiki.st.com/stm32mcu/wiki/Security:How_to_make_your_application_compatible_with_Secure_ManagerSo far the system works fine — I can blink LEDs and run a basic non-secure application without issues.However, as soon as I integrate FreeRTOS and switch the HAL timebase source from SysTick to TIM7, the program immediately stops and goes into the BusFault_Handler() after TIM7 interrupt. Steps to reproduce:1) Follow the Secure Manager tutorial and set up SM provisioning2) Confirm basic GPIO/LED blinking works3) Add FreeRTOS middleware (no other changes)

Hello,I'm currently working on a project using the STM32U5A5VJT6 processor, and I'm exploring the feasibility of implementing WireGuard in a bare-metal environment. I found one mention of WireGuard in this community post [link], however afaik it is an application for an OS based ST product. So I'm looking for more detailed insights.Is STM actively working on any initiatives to bring WireGuard support to processors like the STM32U5A5VJT6, especially for bare-metal implementations?The WireGuard protocol was primarily designed for OS-based systems with kernel support, which makes bare-metal implementation exceptionally challenging. Given the cryptographic and networking demands, has anyone made significant progress or come across alternative approaches that could support WireGuard (or simi

Hello,I am working on the X‑CUBE‑AZURE TFM_Azure_IoT example for the B‑U585I‑IOT02A board and would like to replace the default UART loader with CAN and USB loaders. While the non-secure loader boots and runs correctly, the non-secure interrupts for FDCAN and USB do not trigger. In the application, both peripherals work with interrupts, but in the loader, they do not.To make this change, I modified the loader's non-secure application size to accommodate the FDCAN and USB stacks. However, I am encountering issues with interrupts not firing.I have verified that FDCAN works in polling mode in the non-secure loader application.Environment:Board: B‑U585I‑IOT02A (STM32U585)X‑CUBE‑AZURE: TFM_Azure_IoT (v2.3.0)Toolchain/IDE: STM32CubeIDEWhat I've tried:Adjusted the non-secure application size to fit the CAN and USB stacks.Ensured the peripherals are initialized in the non-secure context.Checked the interrupt enable

We are currently in the early planning stages of developing a PCI PTS/SSF-compliant payment terminal and have selected the STM32U5 series as our target MCU due to its advanced security features (TrustZone, PCROP, HUK, etc.).To ensure we start on the right foundation, we would greatly appreciate your guidance on the following:1. Recommended Software Stack:Which version of STM32Cube_FW_U5 and Trusted Firmware-M (TFM) / SBSFU is currently recommended or validated for security-critical applications like payment systems?Are there any known issues or errata in older versions (e.g., V1.7.0) that we should avoid for certification purposes?2. PCI-Specific Resources:Does ST offer any reference designs, evaluation reports, or application notes specifically tailored for PCI PTS/SSF compliance on the STM32U5 platform?Are there pre-validated secure boot, secure firmware update, or key management implementations we can leverage?3. Documenta

Dear community,where can I find the source code for this generated MX66UW1G45G_STM32H7S78-DK_XSPIM1-SFIx.stldr file?I need to load binary files on an sd/emmc flash passing through the OEMiRoT boot that loads the specific external loader I want to implement based on this MX66UW1G45G_STM32H7S78-DK_XSPIM1-SFIx example.  I have already implemented a custom external loader for my sdcard which works fine when loading the binary directly from CubeProgrammer or IAR ide (no mapping mode), however it fails to load the external loader in RAM through OEMiRoT bootloader through a UART serial interface with this command:  .\STM32_Programmer_CLI.exe -c port=COMxx br=xxx -elbl "my_loader.stldr" -w my_encrypted_file.bin "my_custom_address". The same command works fine with the above example when the firmware update new binary is loaded in the macronix flash. Thank you for help 

Hello,I am working with the STM32L476 and would like some clarification regarding the One-Time Programmable (OTP) area.From the reference manual, I understand that STM32L4 devices provide 1 KB of user OTP memory (128 double words). I would like to better understand the following:What exactly is stored in the OTP area? Is the OTP region purely user-programmable, or does ST also store factory calibration or security-related data in this region? Is OTP used internally by the MCU for enforcing Flash security mechanisms such as RDP, WRP, or PCROP, or is it strictly for user data? How is OTP protected ? I am trying to understand the architectural role of OTP in relation to Flash protection and secure boot mechanisms.Thank you.

I have created my secure boot demo project on STM32H563ZI using the link below.https://wiki.st.com/stm32mcu/wiki/Security:How_to_start_with_STM32CubeMX_OEMiRoT_Boot_path_on_STM32H563During provisioning, the secure image is signed by the TPC (STM32TrustedPackageCreator) tool. TPC supports the standard MCUboot signing process: calculating SHA256, generating the firmare image signature TLV (e.g., ECDSA256 0x22) using the specified private key, and adding standard TLVs. All these work just fine with the TPC tool.Now, I need to append a full public key (IMAGE_TLV_PUBKEY 0x02) as an additional TLV into the image. And one more layer of TLV (IMAGE_TLV_ECDSA256 0x22) for the signature of this pub key. Does TPC support custom TLVs by changing its config file (e.g., OEMiROT_S_Code_Image.xml)?

Our current product uses the STM32H533 microcontroller and password based Debug Authentication. We have a need to generate a large number of different DA passwords and corresponding OB Keys provisioning data. This is possible by creating our own tool to generate OB Keys .xml files and passing those into the STM32TrustedPackageCreator_CLI.exe tool, but it would be nice to cut out the .xml files and need to use the Trusted Package Creator tool. Given that the input .xml file contains a 'hash' tag and that output .obk file contains 512 bits of seemingly random data, I suspect this is a SHA-512 of the password, however I cannot manually re-create the same hash.  I've attempted padding the password to various different lengths, with various different values, additionally including the additional bytes that are included in the created 'password.bin' file that accompanies the .obk file. What process/data

OTP portion of FLASH is a valuable asset in some STM32 families and represents a convenient place to store things like security keys. For this, it is desirable - and, as it's part of FLASH, also quite logically expected - that setting read-out protection to any level above 1 prevents the debugger from reading it.In RM0444 Rev.5 and RM0454 Rev.5 (the current 'G0 manuals), the following text indicates that this should be the case:The following table appears to indicate the same behaviour:

Hello everyone,I'm trying to disable the TrustZone (TZEN bit) on an STM32L562E-DK development board to leave it in a completely clean state (without protections) so I can use it as a standard MCU. However, I'm encountering errors when trying to modify the Option Bytes with STM32CubeProgrammer, and I would appreciate your help.My configuration:Board: STM32L562E-DKSoftware: STM32CubeProgrammer v2.21.0Connection: Integrated ST-LINK (SWD at 8000 kHz)Current Option Bytes status (initial read):TZEN = 0x1 (Trust Zone enabled)RDP = 0xAA (Level 0, no readout protection)SECWM1_PSTRT = 0x0, SECWM1_PEND = 0x7F (Safe area defined)Screenshots of the complete configuration are attached.The problem:From the STM32CubeProgrammer graphical interface, I can modify and apply changes to almost all Option Bytes (such as safe areas or write protection) without issue. However, when I try to

Hello everyone,I am working on a custom board based on the STM32U575RGT6 (1MB Flash). I am encountering a hard fault (SecureFault) during the initialization of the Non-Secure application after integrating the SBSFU.Context:Hardware: Custom board with STM32U575RGT6.Initial Project: A working application using TrustZone active + FreeRTOS (generated via CubeMX). The Option Bytes were set to a default 50/50 split (Secure/Non-Secure).Goal: Implement a Secure Boot / Firmware Update mechanism.What I did:I used the ST example for B-U585I-IOT02A as a reference.I integrated SBSFU_Boot and SBSFU_Loader into my project folder.I adapted the linker scripts (.ld), postbuild.sh, and flash_layout.h to match the 1MB Flash size of the U575RGT6 (vs 2MB on the B-U585I).In my original application, I replaced the .ld files and startup_xx.s file

I have been looking at the CRA Q&A and was wondering what you you are meaning with the reporting of security incidents 2026-12-11. Do you mean the reporting according to article 14 that enters into force 2026-09-11?

Hi, I'm starting to play with the SBSFU examples provided by ST. I'm trying to build the SBSFU (mcuboot based) example for the STM32L5 which can be found in the STM32SecuWS provided here . I'm stuck trying to build the TFM_SBSFU_boot (partial console output):arm-none-eabi-gcc "C:/STM32SecuWS/TFM/STM32Cube_FW_L5_V1.3.0/Projects/STM32L562E-DK/Applications/TFM/TFM_SBSFU_Boot/Src/low_level_com.c" -mcpu=cortex-m33 -g3 -DSTM32L562xx -DUSE_HAL_DRIVER -DNDEBUG -DTFM_DEV_MODE '-DMCUBOOT_TARGET_CONFIG=<flash_layout.h>' '-DMBEDTLS_CONFIG_FILE=<config-boot.h>' -DMCUBOOT_DOUBLE_SIGN_VERIF -DBL2 -c -I../../Inc -I../../../../../../../Drivers/CMSIS/Include -I../../../../../../../Drivers/CMSIS/Device/ST/STM32L5xx/Include -I../../../../../../../Drivers/STM32L5xx_HAL_Driver/Inc -