STM32 MCUs Security

Hello I want to generate random numbers as using registers, not the libraries.I read the RM0090 and wrote the code at the attachment. But I could not configure the RNG_CLK.So I want to know how to configure RNG_CLK.[IAR Embedded Workbench]

Posted on April 13, 2017 at 09:11I've my application that uses the xCube CyptoLib 3.1.0 (STM32CryptographicV3.0.0_CM4_IAR_otnsc.a)with IAR compiler. Up to version 8.10 of the IAR compiler I never had any warning or error during the build of the project. Upgrading the IAR IDE to version 8.11 I have this error:'Warning[Lt009]: Inconsistent wchar_t size crypto.o(STM32CryptographicV3.0.0_CM4_IAR_otnsc.a) has wchar_t size 16 bits 'Reading the release notes of the IAR 8.11 I found this: IAR Information Center for ARMChanged size of wchar_t in version 8.10 and 8.11Object files following the ARM ABI has a runtime attribute indicating the size of wchar_t.In EWARM version 7.80 and earlier, the size of wchar_t was 2 bytes wide and the runtime attribute was set accordingly.For EWARM version 8.10, the size of wchar_t was 4 bytes wide but the value of the runtime attribute was n

Posted on May 08, 2018 at 17:19Please see the attached .png -Using an STM32F746Within Atollic TrueSTUDIO for STM32, when browsing the SFRs in debug mode, the addresses for the registers in the CRC unit are incorrect.As shown in the .png, the controller has a 4 byte RESERVED2 space, which is not catered for by Atollic, thus incorrect values are shown when debugging.Thank you.#sfrs #crc #bug #atollic #stm32f746xx.h

RDP feature is great but code can be modified via IAP programs so i need an mc that have a secure portion of memory that cannot be overwritten at all and cannot be read by user only my code can read from this portion

Problem: Missing support for use of the RSS through its PublicAPI on STM32H7 Information:Reference Manual for STM32H743/753 and 750Chapter 4.5.2 Root secure services descriptionRSS_resetAndInitializeSecureAreas - missingRSS_exitSecureArea - missingRSS_resetAndDestroyPCROPArea - missingLatest STM32H7 Cube packageSearch "RSS_reset*" (0 hits in 0 files) Search "RSS*" (0 hits in 0 files)Goal: We are using STM32H753-EVAL dev kits and want to run our own SecureBootloader, but for this purpose we would need to be able to configure the RSS using the Public API defined in Chapter 4.5.2. Does anyone has information on the following:A. Why RSS functionality described in Chapter 4.5.2 is NOT part of the STM32H7 BSP?B. Is there Demo code for the RSS functionality advertised for ST STM32

Posted on May 12, 2018 at 19:55Secure Boot and Secure Firmware Update is just awesome. Very excited to use it. However, for whatever reason, the process of setting up and practical usage of it is quite confusing.I've loaded the demo application(s) into Atollic and found that nothing works to the degree that the application notes explain. Have the ''Hands on'' workshop but found it more of a ''load the demo.... see it works'' but little in the way of explanation.I've been using http://www.st.com/content/ccc/resource/technical/document/user_manual/group0/33/ee/5b/6b/c7/43/44/3e/DM00414687/files/DM00414687.pdf/jcr:content/translations/en.DM00414687.pdf as the only reference. 

Hi everyone,I'm developing a safety project and using the STM32F446. To ensure the safety standard, before starting the main code, I need to compare the current flash CRC with the CRC which calculated with SREC. The same structure is being used in another project that has an F3 MCU and it can pass this checking correctly but the F446 can't pass. I see it correctly calculating when it runs step by step so the algorithm is correct and was double-checked. However, something goes wrong when the CRC of all flash is being calculated. What is the problem? By the way, I'm using the default CRC settings for F3, not changing any parameter.Also, I'm developing the project according on XCube Class B.

I am looking for some help with the setup and use of the  Cyclic Redundancy Check (CRC) unit implemented in the SPC56 family of automotive uCs; So far I could not find a single sample of code showing how to configure and use it with one of the different available polynomials. Thanks!

hi, im trying to enable the readout protection and successful in doing so but my application doesn't seem to run after its enabled,after entering this function system reset occurs and my user application doesn't seem to run.HAL_FLASH_OB_Launch ()

I have been asked to find out if release STM3232CubeExpansion_CryptoV3.1.1 is the latest release of this package, and if not please tell me where I can get the updated version. If there is no update, can you tell me if and when one is expected

I have polynomial for CRC 0x8C. And in STM I must write 0x31, because it is rotate.But I don't know, how to convert this value to good value.In binary:0x8C - 0b100011000x31 - 0b00110001I create function:uint8_t ror8_polynomial(uint8_t poly, uint8_t count) { return (poly << count) | (poly >> (8 - count)); }And I call this function:uint8_t test = MP_STM32F7_CRC__rol8_polynomial(0x8C, 6);My new value is: 0x23 - 0b00100011Any idea, what is wrong?

Miro-controller : STM32F767 nucleo board

Posted on May 23, 2014 at 03:03Hi All It is strange but I can't find any code example of how to set up the Ethernet HASH filter for multicast reception. There was a question in 2011 in this forum as to the same but it was not answered - so I will try again. At the moment I am working with the ALL MULTICAST bit set so that all multicast frames are received - the reason being that the HASH calculation is presently making no sense. An example - I join a multicast group 224.0.0.33 and would like to set a multicast filter on the corresponding MAC address 01 00 5e 00 00 21 The CRC-32 calculation of this is 0xe2dae536 - taking the 6 MS bits it gives the hash 0x38 so the 24th bit in the high hash register is set. The result is however no reception on the address. Playing around with the bits in the HASH registers it is found, by trial-and-error, that reception works when the 5th bit in that register is

Our application connects to a server in the cloud and recently we migrated from a proprietary AES256 encryption to Mbed TLS based solution.By default Mbed TLS does NOT offer out-of-the-box hardware acceleration for AES, MD5, SHA etc. By accident I was triggered to look at Mbed OS 5 that includes Mbed TLS as one of its features. In the targets directory of the mbed TLS feature within Mbed OS, I’ve found support for hardware acceleration that uses the STM32 Crypto and Hash peripherals (provided by STM32F7xx_HAL_Driver). In my application this works fine.While using the cipher suite TLS-ECDHE-ECDSA-WITH-AES-256-GCM-SHA384, I was wondering why there is only a aes_alt.c implementation and not a gcm_alt.c implementation to support AES-GCM hardware acceleration by STM32 crypto peripheral (these alternative implementations have a STmicroelectronics copyright notice).Searching the Mbed OS code base for AES, I only found the AES-ECB and AES-CBC modes use the HW STM

Greetings, I'm building an app for an STM32L496. I am trying to get the linker to calculate a CRC32 of the ROM image and place it in ROM. I've read a few technical notes on this, and I'm following the ARM example. The problem is I keep getting the "ielftool error: The string '__checksum' was not found in the string table" message. I am declaring __checksum as extern in my code, which doesn't help. If I remove the extern, then I get a duplicate symbol. The example never defines it, it just has the extern reference. I am using C++, which I suspect is part of the issue. Does anyone know the trick to this?Ricardo 

I am using the STM32F071RB microcontroller and trying to use the en.stm32-cryp-lib to encrypt and decrypt using AES128-CBC. The encryption and decryption functions return expected data when using data that is a multiple of 16 bytes, but don't when the data isn't a multiple of the block size.I read in the user manual that the library uses Cipher-text stealing when the data isn't a multiple of the block size, but in my application, the data to be sent/received should be padded with 0x00's. I even tried padding the data with 0x00's to make it a multiple of the block size, but that didn't work, either.Any suggestions?

Hi everyone, I'm trying to port mbed TLS to L432KC MCU however I lack some knowledge about TLS, is this MCU capable of running mbed TLS? I already have both Ethernet and Internet parts solved thanks to a SPI Wiznet chip and I know that the MCU needs a RNG source, which it already has, however I don't feel confident after reading something about Cryptographic library and HW acceleration which is not implemented on L432KC as far as I know. Also CubeMX doesn't bring the mbed-tls option for this MCU.I just want to add the TLS encryption layer but I need to know if it will be possible before spending more time trying to port, thanks.

I try this to use this:/* Private function prototypes -----------------------------------------------*/void SystemClock_Config(void);uint32_t CRCtest0 = 0;uint32_t CRCtest1 = 0;//uint32_t CRCtest2 = 0;uint8_t txData[10]={0xF2, 0x10, 0x10, 0xE0, 0x3F, 0x35};uint8_t crcdatatest1 [4] = {0xF2, 0x10, 0x10, 0xE0};uint8_t crcdatatest2 [4] = {0xE0, 0x10, 0x10, 0xF2};int main(void){ /* MCU Configuration----------------------------------------------------------*/ HAL_Init();                         SystemClock_Config();    /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_DMA_Init(); MX_USART2_UART_Init(); MX_ADC1_Init(); MX_CAN1_Init();

Posted on July 16, 2018 at 12:03Does STM32F105RB has CRC function? Why I can't get the stm32f1xx_hal_crc.c in \Drivers\STM32F1xx_HAL_Driver?#stm32f105rbt6-crc

Posted on February 23, 2015 at 12:25I am making a stand-alone SWD programmer for STM32F1 and L1 families, based on STM32F103. For that I have used AN0062 ''Programming Internal Flash Over the Serial Wire Debug Interface'' by Silicon Labs. Everything works fine and the final touch I need to implement is the ability to re-program read-protected targets. However, the procedure to lower the Read Protection (RDP) from Level 1 to Level 0, described in the Reference Manual for STM32F1/L1 requires to read and write into Flash controller registers inside the target, that is prohibited by the Read Protection itself. Does anybody knows a correct way to set the RDP to Level0 by means of an external custom SWD programmer? Thanks! #rdp #swd

Posted on May 31, 2018 at 11:51Hey all!I'm working on a project(on STM32L1) where i have to set the Read/Write protection so no one can access my code,but the actually i want to build such a mechanism where if i want to make a change in code so i can make it by passing a data on the UART or CDC(i.e serially).Can anyone help me out for this!Thanks,Regards.#access-point #stm32l1 #read-write-protection

Posted on June 25, 2018 at 17:44We are testing SBSFU on a 32L476_nucleo board, using the 2-image example project with IAR EWARM.We can reliably build and update the application in the way suggested.We would like the roll-back feature to work properly - we have been introducing deliberate bugs which cause application watch-dogs, and after 3 of these, SBSFU marks the downloaded application as BAD.  So far, so good.However, SBSFU refuses to roll back to the application in the other image slot because the reported version is the same as the new (buggy) application (in this case, 1). From the readme file in the application section of the project:3. Pressing 3 allows to call user defined services running in Secure Engine.As an example, SE_APP_GetActiveFwInfo service is called in order to display the firmware informationlocated in the protected area such as version and size.What is the correct wa

Posted on July 12, 2018 at 13:43Hi, I am trying to use CRYP_AES_GCM example from STM32Cube_FW_F7_V1.11.0 for stm32f769I-eval.  I see, stm32f7xx_hal_cryp.c has two set of APIs. By default the APIs under ' &sharpif defined (CRYP)  ' are enabled. and these APIs seem not supporting GCM mode as HAL_CRYP_Init() is not even setting chaining mode. but HAL_CRYP_Init() under ' &sharpif defined (AES)  ' has some code to set chaining mode.Are APIs under ' &sharpif defined (AES)  ' are also well tested? But Other extended APIs for AES GCM mode are under ' &sharpif defined (CRYP)  ' in stm32f7xx_hal_cryp_ex.c  file. So I  could not conclude which one is right option either ' &sharpif defined (CRYP)  ' or ' &sharpif defined (AES)  '. Ca

Posted on June 23, 2018 at 08:49HelloI am using stm32l152rc controller and I am trying to load a code using a dfusedemo application and during that time my flash  is on RDP level 1.With help of msp my code jump to location 0x1FF00000 which is location of system boot loader.So, My question is  how can I load a new code?here I am attached some screen short which can help to identify my problem.thanks,Swapnil Champaneria#system-bootloader #st-dfuse #rdp-level-1

Posted on July 03, 2018 at 10:11 Helo friends, I try calculate CRC8 in python and compare with CRC in STM And I have a problem. My python CRC is return wrong value. Python script: def AddToCRC(b, crc): b2 = b for i in xrange(8): odd = ((b2^crc) & 1) == 1 crc >>= 1 b2 >>= 1 if (odd): crc ^= 0x8C return crc�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�? And I call this function here: TestValue = [0, 0xAB, 0xFF] check = 0 for i in TestValue: check = AddToCRC(i, check) print(hex(check))�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�? And I get CRC8 in STM32F: 0x8B And CRC from python script: 0xF8 Any idea, how to calculate CRC8 in python for STM32? #crc8 #crc