STM32 MCUs Security

Posted on October 20, 2014 at 13:51I want to make a CRC check over the APP  FLASH area (I use a BIN file) to know that my APP update O.K.For that I have some question.1. Does the IAR has an option of giving me the CRC of he BIN file I made ?2. How can I know when I made a bin file its size so I can know later till where to check on teh FLASH (does the IAR also give me this data)?3. If  no answer for any of the above question is there a application I can use over the BIN file which can give me that data?ThanksBar. #bin-file-crc

Posted on October 14, 2014 at 17:39I am trying to figure out a way to secure a small section of user data on the STM32F437, and keep it in place during reflashing the device. I ideally want to be able to make it so this data is read protected, but the whole device must be able to be updated through a wireless module I have attached to the processor without losing this one particular block of data.Is there any way to achieve this without an external chip to secure the data? #security-read-protection

Posted on July 02, 2014 at 08:54Hello, I have tried ECC_KeyGeneration_SignatureVerification example in STM32-CRYP-LIB with STM32 F407 (toolchain is IAR) But, when ''Generate ECC key pair'' be executed, the status be changed to FAILED (value:6002 RNG_ERR_BAD_OPERATION). Does anyone can execute this example with STM32 F470? How can I fix it? Thank you Naruhodo #crypto #ecc.h #stm32f4 #discovery

Posted on June 04, 2012 at 02:59Hi:   From simpleMAC & datasheet, it mentioned the STM32W has AES encryption h/w module & API.   But how about AES decryption?   It takes long time to fulfill this function in software. And i think it is quit strange if now h/w aes decryption implemented? #whoosh! #lmgtfy #whoosh! #stm32w-aes

Posted on March 25, 2014 at 18:00Dear All, I run into troubles when I try to start up the crypto processor of my STM32F215. After the line 1, the cryptoprocessor peripheral does not start up: line 1: RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); line 2: CRYP_AES_ECB(MODE_ENCRYPT, (uint8_t*)AESKey, 128, CryptBufferIn, CRYPTBLOCKSIZE, CryptBufferOut); It is worth mentioning that I use our own hardware (STM32F215) that has an external 10MHz quartz. AHB2, APB1 and APB2 are all driven by the same frequency : 10MHz. We normally do not use the PLL. I even tried with a AHB2 much higher than 10MHz, it still does not start either. Now, if I use the same 2 lines code on the Eval Board STM3221G-EVAL (STM32F217), it works well. After investigation, the only difference I have seen between both hardware is the external quartz that is not 10MHz but 25MHz and the

Posted on February 10, 2014 at 17:32Hello,I'm currently implementing AES CMAC crypto using the STM32 crypto library from ST and I'm unable to get the example code to work without returning an error.  I'm using an STM32F103.The example encrypt routine in aes_cmac.h is always returning 3103 (bad_context) as the error_status during the AES_CMAC_Encrypt_Finish() function.I can't figure out why it keeps generating this error, I've read through the user guide for the STM32 crypto library and nothing jumps out at me as to why it doesn't like the context.Any help would be GREATLY appreciated.Regards,Tyler Nehowig #stm32f103 #stm32-crypto-lib #aes

Posted on February 26, 2014 at 17:46 Hi! I'm coding for a IAP program using standard procedures as follows: //normal startup JumpAddress = *(__IO uint32_t*) (ApplicationAddress + 4); Jump_To_Application = (pFunction) JumpAddress; __set_MSP(*(__IO uint32_t*) ApplicationAddress); Jump_To_Application(); For firmware update, I can save JumpAddress and stack pointer to SRAM variables before programming to flash memory, but for normal startup with RDP activated, I cann't read it from flash. My question is how can I implement it when Flash Read out Protection is active? (It is OK when RDP is inactive) Do I have to use external memory to save JumpAddress and stack pointer? Thanks! #iap-rdp

Posted on January 31, 2014 at 23:17I have a question about the HW crypto acceleration in the STM32F4 family.  According to Note 2 on p.12 in the STM document ''STM32 Cryptographic Library Package Presentation'' (see here: http://www.st.com/st-web-ui/static/active/en/resource/technical/document/user_manual/CD00208802.pdf )  ''HW acceleration is only available for STM32F1x and STM32F41x devices'' Is this in fact true?  What about the other devices with HW crypto acceleration (e.g., STM32F42x, STM32F43x) ????? Can someone please clarify?  Thank you. #stm32f4-cryptographic-library

Posted on December 15, 2013 at 21:04Hi, After a few days of experimenting and struggeling my SPI application CRC check somehow still does not seem to work. I'm using the STM32F103ZD uC. Master SPI1 sends data and slave SPI2 receives this data. MOSI/MISO/NSS/CLK pins are connected to their equal named pins. Both SPI's are connected to DMA1 using a 16-bit width data path. On both SPI's the CRC is enabled. Master SPI1 sends data, automatically followed by sending the 16-bits CRC. Slave SPI2 receives data correctly and when debugging the RXCRCR register shows exactly the same CRC as is transmitted by master SPI1. However, the status register of slave SPI2 still shows a CRCERR bit set meaning that the received and calculated CRC does not match the received CRC value. But is does. I slightly tend to think that there is some hardware error in the uC but I'm not sure. Is there anybody that has some positive experience with

Posted on January 15, 2013 at 15:42Hi, I use STM32F107. I have to generate a random number. I don't see how to do it :\ Anybody for help ? #random-number #rng

Posted on November 22, 2013 at 17:25I'm having trouble bridging the two pools of information I read on the subject of TLS handshakes and the AES cryptographic processor. TLS is an exchange of a server certificate, a client premaster secret, and a public key encapsulated in the server certificate.  The bit lengths are 2048 usually for the secrets and keys. The AES on the STM32F4 is a cryptographic hash processor that in order to work, in my case, needs a 256bit AES key. I have the impression I want to use TLS_RSA_WITH_AES256_CBC_SHA.  If this isn't proper I welcome a better suggestion.  How to derive the proper 256bit value to put in the cryptographic STM32f4 registers from all the TLS objects?  I even took the time to read on the key exchange algorithms, but I have a hard time identifying which object(public key, private key, premaster secret) is which variable in the algori

Posted on November 12, 2013 at 22:51I would like to use the hardware CRC on the STM32F407 with DMA. However, my data comes in Big Endian, so if I just use the memory to memory DMA setup my CRC does not compute correctly. Is there a way that I can configure my DMA stream to perform a byteswap for me? Section 10.3.10 of the reference manual [Doc ID 018909 Rev 5] refers to unpacking and edian behavior of the DMA stream but I don't understand if any of that is pointing to swapping 4bytes in a memory to memory transfer. Alternately, if I have to use programmed IO, what is the fastest way to swap my bytes and send them off? The following does what I want, but I suspect there is a way to acheive the same thing with far fewer operations.   for(int u=0; u<8; u++) {         uint32_t temp =0;     &nbsp

Posted on October 11, 2013 at 12:38Hi all ,Currently i am trying to communicate with Vending machine through DEX protocol via STM32.But i could not calculate accurate CRC-16 byte so i receive always an error.There are many online calculator about crc-16 but none of them worked for me.Is there anybody worked with crc-16 in c language and in stm32 syntax? #crc-16

Posted on October 07, 2013 at 15:33Couldn't find topic related appnotes ... Is there any? Like Atmel's http://www.atmel.com/Images/doc2589.pdf There has to be a way to make a easy and protected firmware upgrade on STM chips! Or I'm just bad at finding stuff... #bootloader #stm32 #stm32 #bootloader #rdp

Posted on August 29, 2012 at 15:03Hi forum, I'm having trouble getting the CRYP unit working on a ST32F407. First I've tried manually (failed) and -- thinking that I did something wrong -- tried with the ST provided libraries (which also don't work). I'm doing something wrong, I'm very sure, but I can't figure out what. First off: Yes, I have the device properly enabled: [code] RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); [/code] then, I use this: [code]         CRYP_InitTypeDef x;         memset(&x, 0, sizeof(x));         x.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;         x.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB;         x.CRYP_DataType = CRYP_DataType_32b;      &nb

Posted on July 22, 2013 at 22:23I would like to write pages 0-3 when I have enabled readout protection and not to loose other pages in mean time. Is there any possibility to do it? #readout-protection #read-write-protection

Posted on December 18, 2012 at 09:50Hi AllI have an '105 running a bootloader & application.  The bootloader is stable and I regularly release updates for products in the field.  I recently had a requirement to upgrade the bootloader in the field and wrote an application to do this. (The app contains a binary array of the bootloader, and attempts to over-write the original)It all works great until I attempt to upgrade a device which has read protection enabled, which it fails miserably.  After quite a bit of hair pulling I found the following on page 17 on the http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/PROGRAMMING_MANUAL/CD00283419.pdf:2.4.1 Read protectionThe read protecti

Posted on April 23, 2013 at 15:33 Hello everybody, I would like to know if you have already use IELFTOOL to calculate the checksum of your code and to store it in the FLASH. Like explain by IAR and theirs technicals notes, ->I have created a section like this in the ICF file: 1. define block CHECKSUM_TEST { readonly section .checksum }; 2. place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 3. place in ROM_region { ro, first block CHECKSUM_TEST }; and I add 1. --keep=__checksum --place_holder __checksum,2,.checksum,4 line to arguments of IAR ELF linker. If I see the MAP file, I can see the section created and keep: 1. ''P1'': 0x5b70 2. CHECKSUM_TEST 0x08000124 0x2 < Block > 3. .checksum const 0x08000124 0x2 Place holder __checksum 4. ... Now, I would like to calculate the checksum with IELFTOOL. So I tried

Posted on April 09, 2013 at 17:29I configured a SPI transfer with DMA. It's working.Now I would like to add a CRC16 at the end of the frame. I enable the CRC clock and I set the CRCEN bit.The CRC16 is send via SPI link. But I can't check if the CRC is well done or not! Do you know what are the parameters to calculate the CRC?-->polynom: ok-->initial value?-->final xor value?--> final value inversed?The stm used is the STM3L152.thanks ,GF. #stm32-crc-dma-spi

Posted on February 27, 2013 at 09:43Hi,in the AN PM0042 I found that the read protection is activated by setting the RDP option byte.It is critical to me that the code is safe 100%. My question is: does this option byte ensure that my code will be protected 100% ? #flash-rdp

Posted on February 05, 2013 at 07:25Hi Eveyone.            I'm newbie to this forum and I would expect a single response for this post. Actually i want to encrypt the data that is come from LCD Ram. The dats size would be 37kb when i pass this to for encrption i got no response in my Hyperterminal. Before that i've come accross the more errors like L6406E in Keil. That error related to size of RAM, I had increase the size in TARGET tab in keil compiler then error had gone. But i didn't get proper ouput. It's obivious one that i'm struggling in size of RAM. Here i would like to known cryptographic constrains. If i had increase the block size more than 100, not getting proper output.                             I'm pleased if i got clear on this. Thanks in Advance.           

Posted on December 28, 2012 at 00:34Hi, We would like to announce that the CyaSSL embedded SSL library now has support for hardware-based cryptography and random number generation offered by the STM32F2.  Supported cryptographic algorithms include AES (CBC, CTR), DES (ECB, CBC), 3DES, MD5, and SHA1.  For details, please see the original blog post, here: http://yassl.com/yaSSL/Blog/Entries/2012/12/27_STM32_and_CyaSSL_-_Hardware_Crypto_and_RNG_Support.htmlmailto:info@yassl.com with any questions. Best Regards, Chris  #ssl #tls #hardware-cryptography

Posted on December 13, 2012 at 22:31Hi,I am trying to integrate STM32F2 SHA1 support into an existing crypto API that is structured with three main functions:sha_initsha_updatesha_finalIt appears from the STM32F2 SHA1 example code that the HASH processor is meant to be used in one step - for example, making only one call to create a SHA1 hash.  What would be the best way to break STM32F2 SHA1 hashing up between three functions (as shown above)?Thanks,Chris #hash #sha1 #crypto #stm32

Posted on October 01, 2012 at 15:44Hello Is there any difference between the CRC module at STM32F1 Series and STM32F3 Series.? I saw that there are some new registers active and some new features possible ! #crc #crc #crc

Posted on September 05, 2012 at 22:44I have a situation where the registers appear to be set up correctly, but when I put data into a transmit FIFO, the output on the USB wires is a single byte with a checksum of 0x0000. Put many bytes into the FIFO   a - One byte comes out   b - The wrong byte comes out   c - The packet has a checksum of 0x0000 and is rejected by the host. Does anybody have any experiance with this error, or any idea what can cause it? Thanks #usb #back-packets #crc-error