Automotive MCUs

Good morning everyone,I'm facing some trouble compiling a project made by SPC5STUDIO 5.8.1 the project is configured by written makefile and rule.mk file.I tried with the last release (V6) and it's not working after importing the project (I did save after the configuration.xml was updated by the spc5studio ), I have compiling errors make:ex: *** No rule to make target 'LINIF.c', needed by '/obj/LINIF.o'. Stop.I guess there's some procedure to follow in order to upgrade the SPC5 studio configuration.xml file in order to make it work.I would like to try with the previous version of spc5Studio but I couldn't find a way to download it , could someone share a link for that version?Thank you.

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 have used SPC560B54L5 controller. I am enabled UART over LIN but I don't how to configure UART interrupt and how to use IRQ_HANDLER(SPC5_LINFLEX5_RXI_HANDLER) function for receive and Transmit.

Hello, there may be mistake in ST library. In reference manual registers are like that.In the library SEMA4_RSTGT has two different addresses for read and write but those are in the same address.

how to use UARTto receive data on interrupt instead of using this api (sd_lld_read) as this works in blocking mode in while loop.Micro is SPC560P50L3.Is there is an example to use the Uart Rx on interrupt.As we use this method in Stm32.

Hi,I have configured 5 CAN Rx messages using Dedicated Rx buffers. In between running, I am losing CAN Rx message reception. DRX flag in the IR register is not being set once the problem occurs, thereby missing the Rx messages.I need a power cycle or software reset to come out of the situation.Please can somebody help me to solve this issue? Your help is much appreciated as this is an urgent issue to be fixed in our project.Best regards,Sreejith

Posted on February 28, 2018 at 08:40       My company is working exclusively with Linux, and we have interest in the SPC5 MCUs. But I couldn't find any toolchain for Linux. the SPC5-STUDIO is based on eclipse and claim to be an 'OpenSource Integrated Development Environment' so I was really expecting to find it on Linux, but the download page only provide a Windows binary. Is there any solution for Linux users ?   #spc5studio #linux

if you configure one CDTM.DTM right after one TOM and use it to generate TOM_OUT and TOM_OUT_N, what is the smallest dtz interval you have been able to achieve?if I set the DTM to be clocked with SYS_CLK (100MHz), still the dtz gap can't go anything smaller than a 5usec resolution (i.e. 0, 5usec, 10, ..). Are we sure about that (DTM clocked @100MHz)? By using another TOM channel and comparing edges (knowing how the DTM_OUT is generated from the original TOM edges), it looks as if the DTM is clocked at 200KHz only (but I may well be wrong on this)This is both odd and funny at the same time since the SPC5Studio GTM wizard configuration page computes and shows correct intervals out of DTM channel RELRISE and RELFALL register values the user fills in. 

I am using SPC58EC. When I compile same code with GNU and GHS(Green Hills Software) I see different results.int main(void) {     uint8_t mode;   MC_ME.PCTL[15].R = (uint8_t)18; mode = (uint8_t)MC_ME.MCTL.B.TARGET_MODE;   //SPCSetRunMode /* Clearing status register bits */ MC_ME.IS.R = 0x3FU;   /* Starts a transition process.*/ MC_ME.MCTL.R = (mode << 28) | 0x5AF0UL; MC_ME.MCTL.R = (mode << 28) | 0xA50FUL;   /* Waits for the mode switch or an error condition.*/ while (MC_ME.IS.R == 0U) { ; } /* Check if no error during mode switch */ if (MC_ME.IS.B.I_MTC != 1U) { while(1); }   SIUL2.GPDO[88].R = 0; SIUL2.MSCR_IO[88].R = ((2 << 24) | (1 << 23));   SIUL2.GPDO[89].R = 0; SIUL2.MSCR_IO[89].R = ((2 << 24) | (1 << 23));   /* Application main loop.*/ for ( ; ; ) { SIUL2.GPDO[88].R = ~SIUL2.GPDO[88].R; SIUL2.GPDO[89].R = ~SIUL2.GPDO[89].R; for(long i=0;i<1000000

Hello, I am using SPC58EC-Disp board. Core2 is already active and has timer interrupts. I need to set a timer interrupt in Core 0. I am trying use PIT0 and PIT0 configuration is done by Core2 so I think I only need to do PIT0 Channel settings. Two cores are using same vector table but different IVOR tables, I can set PIT0 Channel2 interrupt for Core2 from Core0, Core2 handles that interrupt very well. When I set same interrupt for Core0 from Core0 it goes to IVOR1. Let me explain this way. If I change first red area like 0x2000 | 4 to set interrupt for Core2, interrupt and Core0 work well or if I don't enable interrupt in second red area interrupt doesn't work but Core0 is workin

Please help to advise whether encounter this ​kind of issue as per below picture for reference as both part no. are still active in STM website which different in memory size.

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SPC58EC has one Interrupt Controller which supports two processors. You can give different vector tables for each core. Let's say two cores are active and one external interrupt (ADC, Timer) happened, what will be the process after this? Which core will run the interrupt handler? Thanks in advance.

I want to use the PE7 pin of SPC560B to detect analog quantity​This requires reusing it as an ADC input pin​How should I configure him?

On spc560b MCU,I use PE [7] as ADC input,But why can't I read the analog quantityThere is no problem with the hardwareHow to configure the software part

we are trying to use LONG_FUNC_RESET as a fault reaction. However, I have a problem: how to read fault information, such as which fault channel lead to this long functional reset, after reset? From the FCCU RF_S/ N2FF_STATUS register?To analysis this, I took the test:I used Fault Channel #8 for the test, set to LONG_FUNC_RESET, Reset occurs after running the software. The cause of the failure cannot be observed from the RF_S register. The expected result should be the bit position 1 corresponding to Fault Channel #8 (RF_S0 256), not always the default (RF_S0 128, RF_S2 1048576); For the always the default, I set all faults to NO_RESET, and RF_S reads still as above after every time it is reset.

Hello,I am currently working on SPC58NG84E7 controller with SPC5 studio.I want to read the cause of reset in main routine.In the reference manual, it is mentioned RGM register (RGM.FES & RGM.DES), which will help the controller to identify the type of reset.I tried to read the RGM register in the beginning of my main function, but every time I am getting 0. I observed during debugging that, before entering into main routine, these registers are getting cleared. So, how to get the reset cause in main routine?Regards,AVM

Hi all!!!I have a problem with GTM / TOM and eDMA.I am using a SPC58-BERNINA (STEVAL-TTM004V1) and SPC5Studio.My goal is to start a copy via eDMA channel when an interrupt of a TOM channel is triggered (suppose CN0 == CM0).In my example I am using GTM TOM1-CH7.Reading table 40 of paragraph 7.3.6.6 I saw that GTM_TOM1_IRQ7 is part of DMACHMUX_3 line 39 so I have chosen eDMA's channel 48 and I initialized DMACHMUX_3 with source 39 (27h).In the same project I am using other eDMA channels, the "start" of which is determined by the ADC_SAR_***_EOC without problems.Del TOM I have enabled interrupts and I have verified that the interrupt is actually called. However, I cannot direct this signal to the eDMA.It should be very simple and straightforward, DMACHMUX has a lot of GTM inputs, but I couldn't.Can someone help me?Thanks,Gionatha

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Hello,I am currently working on the SPC560b60 platform for my automotive application.I'm using a AUTOSAR CAN MCAL from ST. But i'm having trouble in initializing the CAN channels.The CAN channels seem to be always in a low power mode inspite of enabling and setting a proper baudrate configurations. I'm attaching a snapshot of the FLEXCAN registers after the initialization.Requesting you for a short debug session, to understand the issue in detail.Please let me know, if you would need any further info.Thank you for your help in advance.

Hello,I have similar problem with the SP570S-DISP board as described here:https://community.st.com/s/question/0D50X0000ArRejNSQS/spc570-can-outputs-bad-frame-independent-of-frame-parametersMy Configuration: 250KBaud, 16Tq, Sample-point=75%, XOSC 40MHz, CAN_clk 40 MHz, V_ext=12V/VDD_HV_IO=5V, Vector VN1610+CANoe running, 120 Ohm on both sides, ID=0x135, Data={0xAA, 0x55, 0x00, 0x00, 0xAA, 0x55, 0x00, 0x00} DLC=8. Clock settings:/* Setting the system dividers to their final values.*/ /* * b0 : DE = 0b1 enable divider * b9-15 : DIV (Divider is DIV + 1) */ /* System clock 0 divider */ MC_CGM.SC_DC0.R = 0x80000000UL; /* System clock 1 d

Is it possible to not have a filter when receiving CAN messages? I want to create a gateway and transfer ALL messages from one CAN bus to another CAN bus. Do I just have to add 1000 messages to my list of allowed messages to ensure everything is accepted?

I am doing my thesis on Bernina SPC58NN84x and I am trying to implement a CAN bus between the two CAN Subsystems, so that one of them is receiving and the other is sending, but when I do this the CAN TX doesn't recognize the success of the sending and always returns that the value of TXBTO register = 0 (the register responsible for indicating the success of sending) I have two questions in my case:1- how does the transmitter know that he has sent a message successfully? is it hardware or software or something else combined between them?2- does CAN TX knows automatically if the message is sent correctly or should I make some code (e.g if condition) that makes it realize that the message is sent correctly?Note1: the Register TXBTO is a Read-only register and I didn't find any register that can tell CAN that its message is successfully sent.Note2: I am using a logic analyzer and the messages (at least part of them) are