FIFO Fails to Clear on Abort - Slave SPI with DMA - STM32L451RE In a project using the STM32L451RET6, SPI3 is configured as follows* Full Duplex Slave* Hardware NSS Disable* Frame Format Motoroloa* Data Size 8* CPOL High* CPHA 2 Edge* DMA: * SPI3_TX Ch2 Mem to Per, Priority Low * SPI3_RX Ch1 Per to Mem, Priority HighThis works fine for a fixed packet length. Sometimes, however, the master may send a shorter packet (i.e. less than BUFFERLEN). In this case, it is necessary to end the slave SPI receive session and process the master's command. Consider the following code snippet:#define NSS (HAL_GPIO_ReadPin( NSS_GPIO_Port, NSS_Pin ))
#define BUFFERSIZE 16
uint8_t SpiTxBuffer[BUFFERSIZE], SpiRxBuffer[BUFFERSIZE];
typedef enum
{
Idle,
Wait,
Done,
WaitForNSS,
Error
} State_t;
State_t State = Idle;
int main(void)
{
/**
Usual MX boilerplate here.
STM32L451REx
SPI Slave on SPI3 with DMA, 8 bit data, soft NSS
*/
while(
