STM32 MCUs

Discrepancy between AN5967 and MB1940 schematic regarding VDDA18PMU / VDDSMPS connections in external SMPS mode Hello ST Team,We have a custom board based on the STM32N657X0H3Q, designed using the MB1940 (Nucleo-N657X0Q) schematic as reference. The board has been fabricated and assembled, and we are currently in the bring-up phase.During bring-up we encountered a failure on the external SMPS path (TPS62088YFP) used for VDDCORE generation. The external buck failed with a shorted high-side FET, driving 5V directly onto the VDDCORE rail. After investigation, we recovered the board by removing the failed external buck and switching to the on-chip internal SMPS, which is currently working correctly and supplying VDDCORE at 0.810 V.While reviewing the power supply architecture during this debug, we noticed a discrepancy between AN5967 (Getting started with hardware development fo

Hi,I'm trying to setup HSO on the G431, I used the B-G431B-ESC1 board as a starting guide. I'm trying to use differential sensing with internal OP-AMPs and internal PGA. I have split the currents and phase voltages across ADC1 and ADC2 but I still cannot get the HSO option to show up with MC workbench. I'm using the latest version. I have attached my board JSON file, any guidance will be appreciated.Thanks,Ray

I am currently working on the STM32N6570-DK board and need guidance on FSBL configuration, multi-layer project structure, and external flash programming.Issue 1: FSBL Peripheral ConfigurationI enabled multiple peripherals in FSBL:USART1, I2CBSPXSPI1, XSPI2CSI, DCMIPPVENC, JPEGAfter enabling these, I am getting an "unsupported relocation" error.Kindly guide:Which peripherals are recommended to enable in FSBLWhich peripherals should be initialized in the Application layer insteadProper distribution of initialization between:FSBLApplicationExternal Memory LoaderIssue 2: Multi-Layer Project UnderstandingCurrently, the project has:Three separate layers (FSBL, Application, External Loader)Each has its own startup file and main function

Hi,We are currently developing a solution based on the STM32WBA65RIV6 MCU, and we would like the internal RTC to remain active while the MCU is powered down.We assume that this is possible, and we would like to clarify the following points:For how long does the RTC retain its values after the MCU is powered down (by default)?Is it possible to connect a backup capacitor or battery to supply only the RTC or part of the MCU in order to extend the retention time?We also want to know if there is any documentation available on this topic. We have not been able to find detailed information.Thank you in advance.Best regards,Luis

Hi,I am working with the STM32WB5MMGH6TR and would like to achieve the following:Stream GATT data to a mobile phoneSimultaneously play simple audio to BLE earbudsThe audio requirement is modest: a tone that rises and falls in a sine-wave pattern (no music, no complex audio, no high-quality audio). The frequency should sweep between 500 Hz and 2 kHz, with a modulation rate of up to 60 Hz.Is this feasible using the standard ST BLE stack for the STM32WB5MMGH6TR? The key requirement is that both operations run concurrently.If it is possible, could you please outline the recommended approach?Thank you as always.

Hi all, I am trying to implement simple USB-FS communication on a BlueCoin board (STEVAL-BCNCS01V1). I am following the official STM tutorial on USB CDC and referencing the official SW package for BlueCoin. So, for USB I need PLL source from HSE clock: BlueCoin schematic shows that there is a crystal oscillator @16Mhz (NDK NX2520SA) installed directly on the board, so I configured RCC HSE as Crystal/Ceramic Resonator; the problem is that the function HAL_RCC_OscConfig(&RCC_OscInitStruct) in SystemClock_Config retrieves HAL_TIMEOUT as a result. T

Hello,My end node activation mode is OTAA, and is supposed to enter shutdown mode and wake up after a specified period of time period, in order to save power, the end node should skip joining the network at every wake up. I was able to skip the joining process by switching the activation mode from OTAA to ABP after the first join process, but after that, the server did not receive every packet sent from the end node like it used to when i was working with OTAA I doubt this is a good solution since a lot of packets are lostMy questions are:1) What do you think of my solution? is it missing something?2) What are my options if I want to stick to OTAA while skipping the joining process?3) Should I just go with ABP?

Can force a specific DR for LoRaWAN?I tried using: uint8_t custom_dr[7] = {0};custom_dr[3] = 1;lorawan_api_dr_strategy_set(USER_DR_DISTRIBUTION, STACK_ID);lorawan_api_dr_custom_set(custom_dr, STACK_ID);   but did not work.

OverviewDebug Authentication Discovery occasionally succeeds in CLOSED state, but Full Regression fails (“Unable to boot on RSS_DA” / “Unable to detect DBGMCU Mailbox”)Get ready for the stm32 safari! Product / Environment- Board: Custom based off of STM32H7S78-DK (MB1736)- MCU: STM32H7S7L8H6H- Debugger(s) used: STLINK-V3SET- Tool: STM32CubeProgrammer v2.19.0- ST-LINK FW: V3J17M10B6S1- Board setup used during recovery attempts:- tried altering Boot0 (boot from RSS/system flash)- tried manual reset- tried low SWD speed and hardware reset modes Summary of the issueI was attempting to recover the board after secure configuration experiments. The board was originally reachable over SWD, but after running the **`ROT_Provisioning/DA/provisioning.sh`** flow from the

Hi everyone,I’m currently working with STM32 Secure Boot and Secure Firmware Update (SBSFU) and integrating it with my custom application. I’m trying to design the project in a modular and scalable way for long-term use, and I would really appreciate some guidance from those who have worked with SBSFU in production. Current ScenarioMCU: STM32 (Cortex-M series)Bootloader: SBSFUApplication: Custom firmware using HAL, middleware, and CubeMX-generated codeDevelopment tool: STM32CubeIDE Challenges I’m Facing1. Shared Drivers & Middleware

Hi Team,I have successfully integrated and run SBSFU with my custom application, and it is working as expected.Currently, I am transferring the .sfb file .via USB to the DWL_SLOT. Once  the transfer is complete, I trigger a reset using    NVIC_SystemReset(), and the process works fine.I have a few questions regarding the .sfb header. It contains fields such as:FW Tag (SHA-256)Header SignatureFirmware Size (FwSize), etc.My questions are:Using FW Tag (SHA-256) for validationIs it possible to use the FW Tag (SHA-256) to validate the received image in the DWL_SLOT befo

Hello I'm trying to wire up the STM32G0B1CET6N and I don't know how to use the VDDIO2 pin. What is it for and how should I wire it?

Hello!I have a custom board with STM32F746VGT6 MCU, LAN8742A Eth PHY and Ethernet socket. I would like to implement MQTT communication in my project with my board as a client. I am familiar with LwIP and FreeRTOS and use both of these libraries in my current program.I already tried using WolfSSL and WolfMQTT (and succeeded to some degree), but it wasn't very pleasant experience and I had to manually copy and change many files to make it work. I want to rewrite the MQTT implementation as the current one doesn't work very efficiently, but I don't really know where to start. I'm grateful for all suggestions!

Hello,I am trying to port the official BLE_Ota example from STM32CubeWB (WB55 project) to an STM32WB30 device, but I am facing multiple compilation issues after importing the project into STM32CubeIDE.After configuring STM32_WPAN and generating the project for STM32WB30, I get many errors such as:RTC_HandleTypeDef unknown typeIPCC undeclaredFLASH_ECCR_* undeclaredSCB_* undeclaredLL_* functions not declaredHAL and LL drivers missing or inconsistentIt seems like the project is not correctly recognizing the STM32WB30 device definition, and many peripherals (RTC, IPCC, FLASH, RCC) are not properly included or enabled.I already tried:Adding STM32WB30xx define in the compiler preprocessorEnabling STM32_WPAN middleware (BLE stack full mode)Checking stm32wbxx_hal_conf.hHowever, the issues persist and the project still behaves as if it is partially configured for STM32WB55.My questions are:

I want to vary the duty cycle of two adjacent DAC values of an STM32G473.  I am using DAC1 channel1 and channel2 for the output. I want to load DAC1s DHR12Rx registers via DMA when TIM3 hits output compare values.  I set up a memory to peripheral transfer for each TIM3 channel and set the CMAR and CPAR registers to the memory location of the DAC values and the peripheral addresses of the DAC DHR12Rx registers.   I have been able to make this configuration work for making the TIM3 OC events trigger loading of TIM20's CCR registers from memory, but so far, the DMA transfer won't load the DHCR12Rx registers for the DACs.  Are there additional configuration settings to make this work?  CubeIDE\HAL has configuration options for initializing the DAC in DMA mode, but I need multiple triggers the make the duty cycling work.   

HiI've been trying to understand what level of support is available for the H573 security features in Zephyr RTOS with mcuboot but either can't find any information or no one replies to my comments.I have a Zephyr sysbuild build working where mcuboot starts, validates the singed application in slot0 and proceeds tp boot from slot0.What I can't find or confirm is if that security features of the STM32H573 are being used or not. There doesn't seem to be any configuration relating to enabling or disabling the features.Are the security features enabled in Zephyr for the H573?I'm using the latest 4.2 version of Zephyr.CheersDave

I’m currently working on implementing and testing Flash ECC on my controller. According to the datasheet, the device supports ECC, and I can see that it is managed through the FLASH_ECCR register. However, I’m facing some difficulty verifying whether ECC is functioning correctly. Specifically: I am unable to find any ECC-related flags in the FLASH status register. I’m not sure how to intentionally generate an ECC error to validate my implementation (e.g., to confirm that error handling via NMI/interrupt is working as expected). Could anyone please guide me on how to reliably trigger a Flash ECC error for testing purposes on this controller? Any suggestions, references, or example approaches would be really helpful.

Hi, I'm working on a ESL project using STM32WB09. In order to reach greater distances, is it possible to use the CODED PHY ? Thank you

Dear Community, dear STMicro, I'm trying to encrypt data on an STM32WL55JC device using the STM32CubeExpansion_Crypto_V4.5.0 library and then using Python on the PC to decrypt it again.I've taken the example code for RSA encryption from the librarySTM32CubeExpansion_Crypto_V4.5.0/Projects/NUCLEO-WL55JC/Applications/RSA/PKCS1v2.2_EncryptDecryptand adapted it.I've created an RSA 2048 bit key on my PC using this code:private_key = rsa.generate_private_key( public_exponent=65537, key_size=2048) pem = public_key.public_numbers() public_exponent = ["0x%02s" % e[i:i+2] for i in range(0, len(e), 2)] n = "%X" % pem.n n = "0" + n if len(n) % 2 == 1 else n modulus = ["0x%02s" % n[i:i+2] for i in range(0, len(n), 2)] f = open("pub.c", "w") f.write("public_exponent[] = {%s}\n" % ", ".join("%s" % s for s in public_exponent)) f.write("modulus[] = {%s}" % ", ".join("%s" % s for s in modulus)) f.c

I'm working with the STM32G4 series and using the backup registers to store time data that persists across power cycles. I have a question about VBAT brownout behavior that I cannot find explicitly documented in RM0440 or the datasheet.Background:Both RTC and backup registers are in the VBAT power domainI'm using a signature in backup registers to detect VBAT lossThe signature check works fine for complete power lossMy Question:Is it possible for VBAT voltage to drop to a level where:The RTC stops functioningBUT the backup registers still retain their contents?In this scenario, my signature check would pass (registers retained), but the time would be invalid (RTC stopped counting).Do the RTC and backup registers have the same minimum VBAT voltage threshold, or can backup registers survive at a lower voltage than the RTC requires?If VBAT brownout can cause RTC failure while backup registers persist, d

Hello,I'm designing a 2 layer PCB using STM32WL for LoRa operations at 433MHz and need a review of my RF layout. The board is JLCPCB 2 layer standard FR4, 1.6mm thick 1.46mm core, 1oz copper, 50Ω microstrip at ~2.8mm width, about 38mm long. I have placeholder caps/inductor to be populated after board fabrication. I am seeking expert opinion for:Trace width & impedance - does 2.8mm yield 50ohm given FR4, 1oz copper, and 1.46mm dielectric height?Critical length - Are there implications for 38mm length on transmission-line behavior?Taper - Taper starts 5mm in. Are there optimal lengths for tapers? Should I taper for shunt pads?Stitching vias - Recommendations for via spacing for this trace width? Every 5-8mm?Test points - Recommendations for RF test points without effecting impedance?Any other best practices or tips would be helpful. I thank you for any guidance.Best, John

I am trying to integrate Crypto lib to NUCLEOF303RE Board, Any guide or any suggestions would help 

Hi everyone,I’m working on a 4-layer PCB design using the STM32WL (based on the Nucleo WL55JC reference design).For the RF section, I followed the same layout approach as the Nucleo board, including the layer stack-up and RF trace widths.The only difference in my design is that I have some GPIO signals routed close to the RF section. These signals are routed on the 3rd layer, while I am still maintaining solid ground planes on the 2nd and 3rd layers underneath the RF section.I would like to clarify:Is it acceptable to route non-RF signals on the 3rd layer near the RF section if solid ground planes are maintained?Are there any risks (e.g., noise coupling or RF performance degradation) with this approach?Additionally, if I modify the layer stack-up:What parameters need to be adjusted (e.g., RF trace width, impedance matching, ground reference)?Are there any recommended guidelines for maintaining RF perf

Hallo,is it possible to detect in my code whether it was just loaded and started under debugger? The code should behave deifferant as usual because flash loader writes into RAM and .noinit section is modified because of this.I have already checked RSR register. It looks the same as after software reset: CPURSTF, PINRSTF and SFTRSTF are high.Moreover RSR gegister is independent from debug configuration: Debugger / Reset behaviour. I use ST-LINK v3 with ST-LINK GDB server. 

First and foremost, they aren't perfect. The code has tons of work left. But it took me SO long to get ANY i2s audio data from my guitar to my computer, the major hurdle being mostly the lack of USB Microphone drivers provided by the stack.Now that I've made them, and I am pretty sure it's the other parts of the code that are at fault for the clock drift, I am sharing it in hopes that it will help someone else who was in the same boat I was.This is designed for the STM32 to be the SLAVE to a CODEC with Full-Duplex mode support (4-5 wire bidirectional I2S Standard, 16 bit 48k. I know, nothing to call home about, but it is the simplest to get working) Try your luck with your specific CODEC, maybe you can configure things differently and get it working right. On the PCM3060, this was the best I could manage.I have no field experience, no college degree, I am just persistent. If I can do it, you can too. Don't give up. I know I haven't, this is