STM32 MCUs Embedded software

I've adapted the NUCLEO DRP1M1 reference design to build and compile for our Custom STM32U5A9 board, and when I run it, iit gets through these relevant pieces:MX_GPDMA1_Init();MX_UCPD1_Init();MX_TCPP_Init();But then inMX_USBPD_Init() is seems to hang in the Call to:USBPD_CAD_Init() which is part of the compiled STM_USBPD_Library. Running a debugger and working my way backup the call stack, it appears that the library calls CAD_Init()which ultimately callsUSBPDM1_AssertRd(PortNum)where the debugger falls apart. AssertRd has at the beginning the 2 below callsLL_UCPD_TypeCDetectionCC2Disable(Ports[PortNum].husbpd);LL_UCPD_TypeCDetectionCC1Disable(Ports[PortNum].husbpd);LL_UCPD_TypeCDetectionCC2Disable(Ports[PortNum].husbpd); <- appears to work fine.LL_UCPD_TypeCDetectionCC1Disable(Ports[PortNum].husbpd); <- stops functioning.husbpd points the appropriate address

hello ST Community, I'm developing the bootloader for the STM32H755 microcontroller from a specific flash memory address of 0x08010000. I also modified the USER_VECT_TAB_ADDRESS definition in the file 'system_stm32h7xx_dualcore_boot_cm4_cm7.c', as follows: /************************* Miscellaneous Configuration ************************/ /* Note: Following vector table addresses must be defined in line with linker configuration. */ /*!< Uncomment the following line if you need to relocate the vector table anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic remap of boot address selected */ #define USER_VECT_TAB_ADDRESS #define FLASH_BANK1_BASE 0x08010000U #if defined(USER_VECT_TAB_ADDRESS) #if defined(CORE_CM4) /*!< Uncomment the following line if you need to relocate your vector Table in D2 AXI SRAM else user remap will be done in FLASH BANK2. */ /* #define VECT_TAB_SRAM */ #if define

Hello all, I explain you my problem the best I can.   I have a project with the MCU STM32U575RGT6 The project has TouchGFX and FreeRTOS. After the initializations of the peripherals, I have the next calls, so the while(1) in main.c is not executed. As you can see in the next image. So for the moment the only main loop I have detected in the application is the timer interruption.

I have changed the ThreadX system timebase on an STM32H7 from 10 ms to 1 ms (i.e., the RTOS tick is now 1 ms). The application is quite large and makes extensive use of ThreadX services such as thread delays, semaphores, mutexes, event flags, and timeouts in various system calls, all of which are specified in ticks. With this change, the real-time duration of existing delays and timeouts is effectively reduced (for example, a delay that was previously 1 second now becomes 100 ms), so I would like to understand whether these values need to be scaled accordingly or refactored using time-based conversion macros to preserve behavior. In addition, the system uses NetX Duo, which runs on top of ThreadX, and I would like to confirm whether NetX Duo fully depends on the same ThreadX tick and whether changing the tick period to 1 ms has implications for network timing, such as TCP timeouts, retransmissions,

I am currently developing CSI using the STM32N6. I would like to study the project at the following link: https://github.com/STMicroelectronics/STM32N6-GettingStarted-ObjectDetection/blob/main/Middlewares/stm32-mw-camera/Release_Notes.mdHowever, the release notes state "Support for the STM32N6570-DK board only." Does this mean it is impossible to develop this project or related CSI projects on the NUCLEO-N657X0-Q?please help me

Hi all, I am trying to bring up a new custom board with an STM32H7R7 and external flash as well as external PSRAM. While I managed to get the external flash working after some try and error, the external PSRAM seems to be more stubborn. The board uses a IS66WVO8M8DALL-200BLI from ISSI (https://www.issi.com/WW/pdf/66-67WVO8M8DALL-BLL.pdf)  The PSRAM is connected to XSPI1 in OctoSPI mode. The XSPI clock is configured to 133MHz. At the moment the MPU is completely disabled to not having to debug several things at once.  The MX_XSPI1_Init() currently looks like this: static void MX_XSPI1_Init(void) { /* USER CODE BEGIN XSPI1_Init 0 */ /* USER CODE END XSPI1_Init 0 */ XSPIM_CfgTypeDef sXspiManagerCfg = {0

Hello,I need to sync the stm32n6 system timer to be used as PTP master. According to the Reference Manual there is a PPS input that can generate timestamp and interrupt: ETH_PTP_AUX_TSBut according to the RM it is not in all models, and I can't find which models it exists and how to map it to external IO. Thanks,Noam. 

Hello, I am currently using the STM32WBA65RI development kit and exploring its low-power modes. I have run the STOP2 mode example and, according to the datasheet, the current consumption in this mode should be around 5 µA. However, I am measuring the current using an external power supply with measurement capabilities (SMU), powering the board through JP2 pin 1 as specified in the user manual. In this setup, I observe a current consumption of approximately 300 µA while in sleep. Could you help me understand why there is such a large discrepancy? What steps are required to achieve the ~5 µA consumption stated in the datasheet? I also have a few additional questions regarding this mode. In the example, the functionHAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI) is used, but it is not clear where STOP2 mode is explicitly selected. According to the official documentation, there are also STOP0 and STOP1 modes, which adds to my co

Thread split from this post. I am using STM32CubeIDE version 2.1.0. CubeMX generates a project for STM32F769I-DISCO without BSP, but the BSP for this board clearly exists in STM32CubeF7 and is used in official examples. Is there a way to add BSP directly from CubeIDE? If not, what is the correct way to integrate BSP into the project? Thank you.

Hi everyone,I'm trying to use OTG in FS Mode with DMA enabled (I know it's not a consistent use case, as FS datarate is pretty low)But still, I changed the code in Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.c :...#if defined (USB_OTG_FS)/* Disable DMA mode for FS instance */if (USBx == USB_OTG_FS){    hpcd->Init.dma_enable = ENABLE; //FGE: try to use OTG FS with DMA enabled}#endif /* defined (USB_OTG_FS) */...But it does not enumerate. This is the only change I brought to the CubeMX generated code Any hints ?ThanksFabrice

Hi, I am using the STM32U5G9 and trying to control a QSPI Flash (MX25L51245GXDI) using the HSPI peripheral. I am confused about which official HAL library and functions I should use for this specific configuration. Since the hardware is named HSPI but the Flash is QSPI, it is unclear which driver is the intended one. Could you please clarify which of the following should be used? HAL_SPI_... (Standard SPI functions) HAL_XSPI_... (Expanded SPI functions) HAL_QSPI_... (Quad SPI functions) HAL_OSPI_... (Octo-SPI functions) There is no stm32u5xx_hal_hspi.c provided in the firmware package, and using HAL_QSPI_... or HAL_SPI_... functions with the HSPI1 instance results in type-casting errors and compilation failures. Please provide the official recommendation on which HAL driver is mandatory for driving a 4-line Quad SPI Flash through the HSPI interface on the STM32U5G9 s

Hi Support Team,   I am currently using the STM self-test library to ensure compliance with IEC 60730 Class B requirements. Specifically, I worked with the example package X-CUBE-CLASSB-G0 v4.0.0 on the NUCLEO-G071RB platform, utilizing the provided STL_Lib.a library into my projects. However, I am encountering an issue related to limited RAM availability. The library appears to consume a significant amount of memory, leading to a global variable corruption. Could you please advise if there is a lighter or more memory-optimized version of this library available that would still allow us to meet IEC 60730 Class B compliance requirement

I am developing firmware with a Boot region and Application region split for OTA firmware update on STM32F469AIHX.[Environment]- MCU: STM32F469AIHX (Max core clock: 180MHz)- IDE: STM32CubeIDE- HAL Library: STM32CubeF4- Flash layout: Bootloader (Sector 0~N) / Application (Sector N+1~)[Problem]When the flash is split into Boot and App regions, the system does not operate correctly at 180MHz.However, setting the core clock to 128MHz works fine.Also, the Application running alone from address 0x08000000 works fine at 180MHz.[What I have already tried]- Reset CubeMX configuration to default, only changed flash memory layout- Verified VTOR is correctly set to APPLICATION_ADDRESS- Verified SysTick_Handler calls HAL_IncTick()- Confirmed uwTick does not increment when running at 180MHz after jump- Removed HAL_RCC_DeInit() / HAL_DeInit() before jump in bootloader- Tried setting SCB->VTOR befo

Hi,I'm getting info on playing mp3 files with my custom Nucleo-U5A9 (originally a NUcleo-U575, I replaced the MCU and added xtal). I'll be using the audio codec TLV320AIC3110 with I2C and SAI from the U5A9. I'll be using ThreadX, FileX an a uSD card. The mp3 files would be in the uSD.I read here about X-CUBE-AUDIO. But the decode spirit mp3 libraries seem to be for the core M3, M4 and M7. Will any of these work with the U5A9 (core M33)? If not, what other options are there?Thanks

Hello,I'm working on the STM32H735G-DK and try to change LTDC pixel format mode on the fly, but it doesn't work. I'm using the BSP example from example board pack in CubeMX for this board. After reset is possible setup the first time pixel format, but whatever I did after it never work. I tried even did full deinit with HAL_Deinit(), but it simply doesn't work. Pckage version is STM32Cube_FW_H7_V1.12.1For example this functionality (changing LTDC pixel format) working without any problem on the STM32U5G9J-DK2. The main() function where I tried doing this looks like:int main(void) { MPU_Config(); CPU_CACHE_Enable(); HAL_Init(); /* Configure the system clock to 520 MHz */ SystemClock_Config() HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); BSP_LED_Init(LED1); /*##-1- Initialize the LCD #################################################*/ /* Initialize the LCD */

Hello,I am using STM32U575RGT6 with CubeMX 6.17 and the bundled X-CUBE-FREERTOS v1.4.0. After enabling USE_TICKLESS_IDLE, I observed that the tick period becomes inaccurate.Specifically, the delay appears to be consistently shortened to about 0.875× of the expected value.void StartDefaultTask(void const *argument) { while (1) { HAL_GPIO_TogglePin(LED_RED_GPIO_Port, LED_RED_Pin); vTaskDelay(400); } }With USE_TICKLESS_IDLE disabled, the delay is approximately 400 ms as expected.Aft

Hi,I am working on a custom Battery Management System (BMS) using STM32L476RG as the MCU, interfacing with an external battery monitor AFE (BQ79656‑Q1).I first validated the MCU hardware and basic firmware by testing the on‑board LEDs and UART communication via test points using USART2. These tests were successful and confirmed that the STM32 configuration and standard UART peripheral are working as expected.After this initial validation, I started implementing the communication between the STM32 and the AFE. For this communication path, LPUART1 is used, while USART2 remains dedicated only for basic UART testing and debug output.As part of this implementation, I took a Single Device Read command frame from a reference software design document for a similar AFE and directly programmed the frame transmission in STM32CubeIDE

Hello,I have STM32F7 controller, using Free RTOS, trying to interface external NOR flash, S29GL128S10TFIV13.I have one source file say testCode.cpp, which I want to move completely in external NOR flash, but every time I ran then code it give Hardfault.MEMORY { RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K EXT_FLASH (rx) : ORIGIN = 0x64000000, LENGTH = 16M EXT_SRAM_HEAP (xrw) : ORIGIN = 0x60000000, LENGTH = 256K EXT_SRAM_STACK (rw) : ORIGIN = 0x60040000, LENGTH = 256K } SECTIONS { .isr_vector : { . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(4); } >FLASH .ext_flash_code : { . = ALIGN(4); _sextflash_run = .; *(.ext_flash_data*) *(.ext_flash_data*) . = ALIGN(4); _eextflash_run = .; } > EXT_FLASH /* 2. SECTION FOR MANUAL ATTRIBUTES (For Arrays) */ .ext_flash_data : { . = ALIGN(4); *(.e

Hello,I was trying to create two heap regions, sing internal RAM and external SRAM. So I tried below, but the code at some point crash and generate hardfault error. Just want to know does the procedure is correct or am I missing something?//in .ld file MEMORY { FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K EXT_SRAM (xrw) : ORIGIN = 0x60000000, LENGTH = 512K EXT_PSRAM(xrw) : ORIGIN = 0x6C000000, LENGTH = 8M } _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */ _Min_Heap_Size = 0x0; _Min_Stack_Size = 0x400; ._user_heap_stack (NOLOAD) : { . = ALIGN(8); PROVIDE ( end = . ); PROVIDE ( _end = . ); . = . + _Min_Heap_Size; . = . + _Min_Stack_Size; . = ALIGN(8); } >RAM .heap_internal (NOLOAD): { . = ALIGN(8); _heap_internal_start = .; . = . + 0x2000; /* 8 KB internal heap */ _heap_internal_end = .; . = ALIGN(8); } >RAM .heap_ext (NOLOAD) : { . = ALIGN(8);

As is well known, the ADC sampling rate is on the order of microseconds, while the display task may only refresh once every 100 milliseconds. In an RTOS, how can the display task and ADC sampling values be synchronized? With such a long display refresh cycle, how are the numerous ADC sampling values handled—should they be discarded or stored in a buffer? If stored in a buffer, would it occupy substantial memory space? How do people handle this issue in actual applications?

I have a project that will be using the LIV4F chip. I downloaded and installed X-CUBE-GNSS1 but its description says it is for the LIV3F. Is it compatible with and will it function with the LIV4F chip? I will be using it on the STM32G474CEU6.Thanks!

I'm failing to enable that Interrupt using " LL_RTC_EnableIT_SSRU(RTC) " on STM32H33.Wakeup timer is set to interrupt every 24h (this is working).Alarm A is configured, but not enabled.Alarm B is not used.RTC is set to BCD mode only.Monitoring SSR register ( via "READ_REG(RTC->SSR)" ) I can see it's counting down from 0xFF ---> 0x00, periodically.Some Internet folks told me to enable TAMP Interrupt as well...and intercept TAMP IRQ handler instaead of RTC IRQ handler. It didn't work.Any help would be greatly appreciated.Thanks.    

Hello everyone,here are my questions:1. Is there any roadmap or community effort to add NeoChrom/GPU2D support to Zephyr?2. Has anyone successfully integrated the STM32 HAL GPU2D driver alongside Zephyr?3. Would it be possible to:- Initialize GPU2D using HAL in the Zephyr application- Patch Zephyr's LVGL Kconfig to expose Nema GFX options- Use LVGL's existing lv_draw_nema_gfx_stm32_hal.c backend4. Are there any technical blockers (interrupt conflicts, clock management, memory mapping) that would prevent this hybrid approach?I'm willing to contribute if there's guidance on the proper implementation approach.Thank you for any insights.

Hello, all my tools are updated to last ones, and software packages too. I start an empty project using X Cube FreeRtos 1.5 (just a default task). Play the soft with debug, and after a few seconds, press "Suspend" button to break the running program. Then, there are a lot of calls to vPortSetupTimerInterrupt function (port.c) in the call stack. The tick is by default 1ms and cpu clock to 250Mhz.  Not sure that is normal? thanks for your help Laurent    

Hi all, There are a few options for mp3 decoding but none seem to be for the M33 core MCUs. Source code seems to be missing too: X-CUBE-AUDIO: the precompiled binaries only seems to support M4 and M7 cores.X-CUBE-AUDIO-KIT: this does not natively have an mp3 decoder.STM32-MP3NL/DEC: this looks like a precompiled spiritmp3dec file for M7. I've spend too many hours looking into this and I'm back to where I started. It looks like the best option would be to use X-CUBE-AUDIO-KIT and add an mp3 decoder to audiochain but how? it needs to support the M33 core and ideally have the source code available. I've also read that some people here have used minimp3. I prefer an option supported by ST and I'm not sure that is the case. Comments/suggestions welcome. Thanks.