STM32 MCUs Embedded software

Hello ST!This is a bug report of sorts, since the `UTIL_SEQ_Run()` function is still marked that it allows nested calls. (I'm looking into the sequencer as delivered with the WBA package.)In the past two years, somebody had introduced an obvious error into `UTIL_SEQ_Run()` function (when they were adding the support for the `UTIL_SEQ_PostTask()` or the `TaskClearList` feature.)Inside the call to `TaskCb` callback, the static variable `CurrentTaskIdx` would be changed by the nested `UTIL_SEQ_Run()` call. Yet, after return from the callback, the variable (now with incorrect value) is used twice (before being set to `UTIL_SEQ_NOTASKRUNNING`). Two years ago when I was reviewing the code for the first time, and the bug wasn't there. (Indeed, the sequencer included with the early versions of STM32CubeWBA package has correct implementation of UTIL_SEQ_Run() that handles the n

I get two errors from here:ret = wolfSSL_connect(g_tls.ssl);if (ret == WOLFSSL_SUCCESS) {printf("TLS handshake OK\r\n");g_tls.state = TLS_STATE_TLS_ESTABLISHED;} else{int err = wolfSSL_get_error(g_tls.ssl, ret);if (err == WOLFSSL_ERROR_WANT_READ ||err == WOLFSSL_ERROR_WANT_WRITE) {} else {printf("TLS handshake failed: %d\r\n", err);g_tls.state =

Hello, Does the stm32n6570-dk has no support for lwip?

Hello everyone,I wanted to ask you about a problem we are having with the combination of the STM32H7 chip and a 16-bit SDRAM memory, AS4C16M16SA.To give you some context, we are reading data from a sensor, a radar, which generates 18432 bytes per frame, and we have 47 frames. So, in each frame, we receive an IRQ and we start the process of reading the data via SPI and DMA. When the DMA has finished copying all the data to an external RAM buffer, we do a memcpy to a larger buffer (in the SDRAM) that collects all the frames.Then, once we have these 47 frames in the SDRAM, we simply copy them to the eMMC memory (configured as a FatFS) with the f_write command.This is where the problem arises: the data we get is not what we expected. Since it is radar data, we have an algorithm that returns images, and they do not match what we should be getting. The key is that we have the same system but with 8-bit data memory, and with this, the data we g

Hi,I have been using OpenAMP on an STM32H755ZIT MCU recently but ran into an issue where the mcu would go into hard fault caused by a bus fault somewhere in virtio code. The issue occurs only after a while, after dozens of messages have successfully been passed in both directions.I haven't been able to exactly pinpoint the violation because i get an IMPRECISERR bus error and have not been able to disable write buffering (I tried with an MPU config which failed and the config register value from https://community.st.com/t5/stm32-mcus/how-to-debug-a-hardfault-on-an-arm-cortex-m-stm32/ta-p/672235, but that doesn't seem to exist on this mcu). I did seem to get the rough area of the fault with the stack trace which pointed me to `uint16_t vq_ring_add_buffer`. Because of the disassembly view and register state before the fault I t

STMicroelectronics Support Team,I am currently working on a project using the ST67W611M1 Wi-Fi module and I would like to request your technical support regarding a platform migration.I have successfully validated the ST67W611M1 using the STM32U575ZI-Q Nucleo board, running the test and reference applications provided in X-CUBE-ST67W61.With this setup, the NCP firmware, AT command interface, and Wi-Fi connectivity are all working as expected.My objective is now to migrate this implementation from the STM32U575ZI-Q (STM32U5 series) to an STM32G0B1RE, which will be the target MCU for the final product.Given the architectural differences between the STM32U5 and STM32G0 families (clock tree, peripherals, HAL configuration, and BSP adaptations), I would appreciate your guidance on the following points:Recommended procedure or reference examples for migrating the ST67W611M1 host firmware from STM32U5 to STM32G0Any known limitations or constr

Hi, in STM32H7 dual core, i have an example of data sharing between the core using ring buffer method, here when caches are enabled, the data sharing is not happening what will be the reason. when caches enabling lines are disabled data sharing is happening.  ring buffer is placed in D3 SRAM        regards. Srinath

Post edited by ST moderator to be inline with the community rules for the code sharing. In next time please use </> button to paste your code and a linker script content. Please read this post: How to insert source code. Hello,I'm trying to use an LCD with ILI9341 chip. I've connected all pins to the LCD and I've set in CubeMX the FMC like this: But when I tried to run the program, all calls from main.c is calling M

I’m working on a project using STM32H7 (Cortex-M7 core) with eMMC and Azure RTOS FileX to manage file systems.The buffer is allocated as:ALIGN_32BYTES (uint32_t fx_mmc_media_memory[FX_STM32_MMC_DEFAULT_SECTOR_SIZE / sizeof(uint32_t)]);During initialization, I call:fx_system_initialize();fx_media_open(&gst_mmc_disk, "eMMC", fx_stm32_mmc_driver, ...);However, the system crashes with a HardFault inside: SCB_InvalidateDCache_by_Addr()which is called from: fx_media_open() ->fx_stm32_mmc_driver() ->mmc_read_data() ->invalidate_cache_by_addr() CopyEdit   

Hello ST Community,I'm working on an STM32H753VIT6 project and need to upgrade FreeRTOS from v10.3.1 to v11.2.0 due to cybersecurity requirements. I've encountered several integration challenges that I'd like to share and seek guidance on.BackgroundCurrent Setup:Working on an STM32H753VIT6 microcontrollerFreeRTOS v10.3.1 with CMSIS-RTOS v2 wrapper automatically generated using CubeMX which works seamlessly out of the boxTarget:Using the newest FreeRTOS v11.2.0 from official repository (preferably without the CMSIS wrapper so future upgrading will be easier): https://github.com/FreeRTOS/FreeRTOS-Kernel/releases/tag/V11.2.0The process:So I followed some guides from the FreeRTOS forums and the ST community

Hi All,I am quite new to bootloaders and I wanted to understand best approach to upgrade the firmware. I will get the firmware from a 4g module and store it in external flash. We are based on STM32U5A5 mcu and it will always use the application present in the internal flash. External flash will have two copies/slots. Current one for rollback and new downloaded one.I am thinking about the following approach. I was wondering if there is anything build-in to do this? I suppose almost everybody must be using the same approach.Is there any stm32 bootloader that can do the same? If custom bootloader is needed i

It seems there's a bug in the HAL library causing data bytes to be mixed with memory address bytes when sending data using HAL_I2C_Mem_Write_IT function. The issue was observed on STM32L162VET6 while using I2C as master at 300kHz speed. It is caused by the condition in HAL_I2C_EV_IRQHandler (stm32l1xx_hal_i2c.c) on line 4808.The issue happens after TXE interrupt occurs (DR is waiting for another byte of data) and your interrupt routine is not fast enough to provide DR with another byte of data, before all bits from SHIFT register are sent out. In that case, a BTF interrupt occurs, causing the code of the HAL_I2C_EV_IRQHandler to go for I2C_MasterTransmit_BTF instead of I2C_MasterTransmit_TXE function. The problem is, that I2C_MasterTransmit_BTF doesn't handle memory address. It only copies another byte of data from data buffer. The issue is invisible when the situation happens while sending out the data buffer. But if it happens during sending out the memory address

Hi everyone,I’m working with an STM32H7S3 microcontroller and an external Octo-SPI NOR flash IS25WX064 from ISSI (datasheet: https://www.issi.com/WW/pdf/25LX-WX032-064.pdf)My goal is to get this memory working with ExtMemLoader (including XIP support). I’ve gone through all the available tutorials and many of the forum threads related to ISSI 25LX/WX devices, but after many hours I still haven’t been able to generate even a single .stldr that doesn’t crash in the STM32CubeProgrammer.A few important points:This does not seem to be a hardware issue. I can successfully communicate with the flash and read the manufacturer configuration/registers via the XSPI peripheral.I have been following the ST tutorials for this MCU family (the ones that use the Macronix flash on the official demo board).I

Hi, I use STM32H7 with STCUBE 11.1.I use RNDIS module  usbd_cdc_rndis.h to communicate with a PC.Sometimes when the PC sends a frame the STM32 replies with NAK, here is the sequence that repeats:SYNCPID OUTAddressCRCEOPSYNCPID DATA0data 30 bytesCRCEOPSYNCPID NAKEOPWhat might be the issue? Can I change the USB interval (CDC_RNDIS_FS_BINTERVAL)?BRJonas

Hello ST Community, I am working on an STM32N6-based board and trying to expose an onboard SD card (SDMMC2) as a USB Mass Storage (MSC) device using FileX and ThreadX. The intended behavior is:When a USB Type-C cable is connected to a Windows PC, the SD card should appear as a USB removable drive with full read/write access. Hardware / Software Setup MCU: STM32N6 SD interface: SDMMC2 (4-bit, polling mode) USB: USB OTG HS (Device mode, MSC class) RTOS: Azure RTOS ThreadX File system: FileX Toolchain: STM32CubeIDE OS on host: Windows 10/11#if (FX_STM32_SD_DMA_API == 1)  /* the SD DMA requires a 4-byte aligned buffers */unaligned_buffer = (UINT)(media_ptr->fx_media_driver_buffer) & 0x3;#endif unaligned_buffer always evaluates to 0 because the buffer is aligned, but this does not resolve the issue. Specific Debug Observation (FX_DRIVER_BOOT_READ)Du

In function LL_RTC_ALMB_SetDay of file stm32u0xx_ll_rtc.h line 2198  Original:__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day){MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),(((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));} Missing x in RTC->ALRMBR __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day){MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),(((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));} Personal opinion: I would recommend compiling code with the -Wall, -Wextra, and -pedantic compiler flags.From my point of view, confidence in the quality of code that contains such easily detectable errors is greatly limited. For this

Hi,I'm currently working on a project using an SMT32G474RET6. We have the X-Cube-STL with us and trying to integrate it into our project. We have followed all the steps as mentioned in the document and we are able to run the test for our software, but it kept failing for CPU in Multiple test and for Flash in Single test. We also tested the example codes on the Nucleo -G474RE, it works there but not with our project.Any idea what could be wrong? what thing should we check to resolve this issue. I have tested the Artificial failing example within our project, and it seem working fine, but the single test and multiple tests are not working.

Hi! I am trying to do a simple communication between nucleo-f411re and nucleo-h753zi board using uart communication. but i am unable to set it up. Is it possible?  If yes, what is the easy way to do that. How the connections and wiring look like? 

Hi,In the GPIO interrupt configuration, the port information is ignored and only the pin number is used for identification. As a result, pins with the same pin number on different ports cannot be enabled as interrupt sources at the same time. stm32_gpio_irq_line_t stm32_gpio_intc_get_pin_irq_line(uint32_t port, gpio_pin_t pin){    ARG_UNUSED(port);    return linenum_to_ll_exti_line(pin);} int stm32_gpio_intc_set_irq_callback(stm32_gpio_irq_line_t li

Hi, I want to start a new project with a STM32H503 (might be), and I read many threat talking about USBX FILEX now on this kind of microcontroller.As it is a bootloader, I do not want to use any RTOS.I use to do bootloader with USB host interface to update the firmware with STM32H7 or STM32F7, but with old stack. Can you please confirm I will be able to develop a bootloader (usb host) to get a binary file on a USB stick storage using USBX and FILEX, WITHOUT any RTOS on a STM32H5 ? Every exemple I found is for device standalone, not host USB.Is there any up to date example with USB host MSC flash stick using USBX and FILEX to start ? Sébastien

Due to more performance requirement, i wanted to change the ThreadX timebase to 1ms. To what i have researched till now i need to make the following #define TX_TIMER_TICKS_PER_SECOND to 1000 which is usually set at 100 which is 10ms. Any idea what else need to be done to make the ThreadX timebase to 1ms other than this or is this enough already?Thanks a lot for guidance.

Post edited by ST moderator to be inline with the community rules for the code sharing. In next time please use </> button to paste your code and a linker script content. Please read this post: How to insert source code. Hi,I was trying to use multiple ADCs in stm32f103c8t6. I have configured seven channels in ADC1 using DMA and ADC2 as single channel without DMA. Both trigger interrupts where ADC2 has the highest priority. The sampling time for the seven channels of ADC1 and single channel of ADC2 is 41.5 cycles and 239.5 cycles respectively. The ADC clock frequency is 10.667MHz. I calculate that ADC1 interrupt is triggered every 35.4us and ADC2 interrupt is triggered every 23.6us. System clock is 64Mhz.

I am working on an STM32 + Azure RTOS project where I need to access the same SD card in two different modes: When the microcontroller accesses the SD card directly, I use FileX with an SDIO/SPI driver. When the SD card is connected to a PC via USB, I use USB MSC (Mass Storage Class) so that the PC can read/write the card. Individually, both functions work perfectly:  FileX can read/write SD card when MCU is accessing itUSB MSC works when PC is connected However, when I try to support both modes simultaneously, the SD card fails to work correctly.There is no reference example from ST or Microsoft showing how to share the SD card between FileX and USB MSC at runtime. My main question: How can I properly share the same SD card between FileX (MCU acce

Hi,I'm using STM32H7 dual core, where the data has to be shared between the cores, so im having totally 21 variables totally 76 bytes, thought of do it like a structure, so where to place the structure exactly for this data sharing. so, this structure should be placed in any linker file of one of the cores or where?if so, thus we have to keep the structure in both the core or whatwhich method is a fastest wat to share the data, like a ring buffer, HSEM.if we use HSEM, we can use that structure or access outside, before calling the HSEM TAKE, or structure values should be assigned only inside after the HSEM TAKEOVER.  regards,srinath

Hi!EDIT: WARNING! This is no real fix... The bug remains...With STM32Cube_FW_F2_V1.9.0 and CDC's /dev/ttyACM0 I had funny glitches on VoidLinux, when i tried full duplex communication (host<>device):some packets never arrived at the USB hostsome short packets had their first 4 byte twiceDeepSeek suggested to choose different endpoints for data in and out... like this:#define CDC_IN_EP 0x81U /* EP1 for data IN */ #define CDC_OUT_EP 0x02U /* EP2 for data OUT */ #define CDC_CMD_EP 0x83U /* EP3 for CDC commands */it seems like those glitches disappeared now... Or i did not dare to test it hard enough...Why is CDC_OUT_EP 0x01U by default, although DeepSeek thinks, that the STM32F207 hardware cannot cope with that, because IN&OUT stream share somehow the same hardware elements, if they are configured for the same endpoint?It was easy to