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I am currently working on a project using Steval mkboxpro and I would like to implement BLE Mesh communication between them. I am still learning and I was wondering if you could give me some guidance or recommend resources on how to do this Any help or advice would be greatly appreciated.

Hello Team,  Since SCB and other core registers are not included in the SVD file for STM32H5, could you please advise on the best way to access or monitor SCB registers (e.g., VTOR, AIRCR, ICSR) during debugging in VS Code with PlatformIO? Specifically, I'm looking for guidance on: How to inspect SCB register values during a debug session (e.g., trap cause, exception entry). Recommended approach to capture trap/exception information like: HardFault status (HFSR) Configurable Fault Status (CFSR) Bus Fault (BFAR) MemManage Fault (MMFAR) Any suggestions for manual mapping or watch expressions in the debugger that would allow me to monitor these registers, since they’re not shown in the peripheral view. Any tips or best practices for bare-metal Cortex-M33 debugging without full SVD support would be greatly appreciat

Created a STM32H743II prj with I2S2 enabled, half-duplex slave receive mode, and DMA1 S0 bounded to SPI2_RX, to work with an ADC in master mode. Can't get data from the ADC ( DMA linked mem area always zero ), while my oscillograph can properly decode the ADC I2S data output pin ( CK & WS pin also connected between the ADC board and the H743 board, and the oscillograph ). In cube, the SDI pin is mapped to SPI2_MISO, PB14. But as a slave, shouldn't the correct SDI pin map to SPI2_MOSI, PB15? So I modified the cubeMX generated code manually, by changing PB14 to PB15 in the I2S2 GPIO initialization sector, and it worked, the DMA linked mem area shows the same value on my oscillograph. Is this a cubeMX bug?

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Hi,I am trying to install ST Edge AI Core 2.0.0 for an STM32N6 project. During the installation process, the installer asks me to specify the ST Neural-Art package archive.However, I cannot find the ST Neural-Art archive on this page:https://www.st.com/en/development-tools/stm32n6-ai.html#overviewI only found the ST Edge AI Core download, but not the separate Neural-Art archive required by the installer.Could you please let me know where I can download the correct ST Neural-Art archive compatible with ST Edge AI Core 2.0.0?Thank you.

Dear ST Community,I’m currently working with an ALIENTEK STM32MP257 development board and ran into an issue when deploying a model converted via the ST Edge AI online tool.The original model is a plant disease recognition model from the ST model zoo (in .tflite format). I used the ST Edge AI webpage to convert it to an .nb model for deployment on my STM32MP257 board. However, when I test the converted .nb model, the inference output is unexpected: it only predicts two classes — “Background_without_leaves” and “Corn__Northern_Leaf_Blight” — both with relatively high confidence. This happens regardless of the input image.In contrast, when I run inference directly using the origi

Added "DHCP" in the title to give the context. Using an STM32H7S78-DK I try to set up the network to join an IPv4 network through DHCP. I did set up the board using CubeMX, standard configuration, MPU activated. FreeRTOS + LwIP Removed all other interfaces I don't need. Made sure the Ethernet clock shows 50MHz The LED's on the RJ45 start to blink (Orange LED blinks with packets exchanged) but I get no IP address. digging in the possibilities I added a simple routine to monitor the DHCP advancements. struct dhcp *dhcp_data = netif_dhcp_data(&gnetif); if (dhcp_data != NULL) { printf("[DHCP] State: %d, Retries: %d\r\n", dhcp_data->state, dhcp_data->tries); } this shows I get stuck in state 6: waiting for an ACK -> what could be behind this? can someone share an .ioc file that sets everything cor

 Hi @Community, I have previously posted the same issue , that i have been working on the STM32H723ZGT6 - Nucelo board on Ethernet LWIP to acheive TCP/IP without free RTOS, Im still facing the same issue that i cant ping the IP.I have tried the GITHUB of STM32CUBEH7 -> APPLICATION ->LWIP -> TCPSEREVR ECHO . Its working perfectly , but cant remake or reuse it due to some library issue , im in a middle of a development of a project. so i tried to take the tcp confing in the example code and reuse it , but that also failed So i tried to remake the all the linker script and searched various Youtube videos , but everything remained in  vain , ill share some screenshots of my configuration , can anybody help me with this , I previously seens several quries that facing the same issue , those who got resolved the issue kindly share your solution and approach with me.  

My situation:Trying to step through/debug a project that will run from the QSPI on the STM32H750B-DK in VS Code (on linux, if that matters). In order to test out the toolchain, I've started with two (separate) workspaces: on has the ExtMem_Boot project, the other the LTDC_Paint demo.What works:A/ Building both projectsB/ Flashing (via tasks.json and STM32CubeProgrammer) the ExtMem_Boot projectC/ Debugging the ExtMem_Boot project via the VS Code debug viewD/ Flashing (via tasks.json, STM32CubeProgrammer and the ExtLoader MT25TL01G_STM32H750B-DISCO.stldr) the LTDC_Paint demo.E/ Launching the debug flow of LTDC_Paint (after modifying launch.json to include the serverExtLoader)What fails:The debugging automatically halts at the Reset_Handler of the startup file, the instruction for loading the stack pointer. But at this point I can't seem to step through it. Even just pressing the run arrow seems to result in a crash, rat

The WL series is great, but unfortunately there aren't any chips with more than 256KiB flash and 64KiB RAM. This appears to be a serious limitation for a SoC with LoRa connectivity.The value proposition of this series is that you pay for one package that provides both connectivity and compute, which is cheaper than paying for 2 separate ICs. I'm personally working on a project where this small memory is beginning to be an issue, and I might end up having to separate those ICs.It kind of seems strange to me that the G0 "entry-level" series comes with much more memory - up to 1MiB / 144KiB.Are there any plans to bring out WL series chips with more memory?Thanks

I am using CUBEMX Version      6.17.0STMCUBE IDE                            2.1.0FW Package name & version     STM32Cube FW_H7 V1.13.0Enabled LWIP ETH With FREERTOS CMSIS2same settings did with cmsis version 1 it's working but with cmsis version2 NOT WorkingI configured on internal Timer TIM1 as soon as I connect Eth Cable program counter not reaching threads & Timer callback / TIM6(systick update).I checked in fault handlers it is not reaching here ETH State in eth handler is (READY STATE --> START STATE)Error code in eth handler is zero.Here I have attached my .ioc fileI have updated flash ld file as per repository code LWIP Debug Messages :

Hi, As per UM3610 « section 7.7 », a "Bootloader limitation" has been found in NUCLEO-WBA25CE1. Please refer to "Workaround" section if you are facing this limitation.

 I am using CUBEMX Version   6.10 STMCUBE IDE                        1.16.0FW version                               F7V1.17.0Enabled LWIP ETH With FREERTOS CMSIS2same settings did with cmsis version 1 it's working but with cmsis version2 NOT WorkingI configured on internal Timer TIM1 as soon as I connect Eth Cable program counter not reaching threads & Timer callback / TIM6(systick update).I checked in fault handlers it is not reaching here ETH State in eth handler is (READY STATE --> START STATE)Error code in eth handler is zero.Here I have attached my .ioc fileI have updated flash ld file as per repository code LWIP Debug Messages : netif: netma

Split from Transmit line stuck high on STM32F415 with MAX3232 - this is a new questionWhat ST board would you recommend? This is not really my realm. Thanks!

Trying to program the option bytes I get the error message shown below. Can someone tell me what is wrong? I have tried with and without the displ and I have also tried with only one option byte at the time.C:\Temp\BMSM-18>"C:\Program Files\STMicroelectronics\STM32Cube\STM32CubeProgrammer\bin\STM32_Programmer_CLI.exe" -c port=SWD -ob TZEN=B4 SECWM1_STRT=0x0 SECWM1_END=0x0 SECWM2_STRT=0x1f SECWM2_END=0x0 displ-------------------------------------------------------------------STM32CubeProgrammer v2.22.0-------------------------------------------------------------------ST-LINK SN : 003F00383234511537333934ST-LINK FW : V3J15M7Board : STLINK-V3MINIEVoltage : 3.29VSWD freq : 8000 KHzConnect mode: NormalReset mode : Software resetDevice ID : 0x478Revision ID : --Device name : STM32H533/523NVM size : 512 KBytesDevice type : MCUDevice CPU : Cortex-M33BL Version : 0xE2SFSP Ve

This error pops up everytime I try creating a new STM32 project when downloading the selected files during the first stages of creating a project. My internet connection is fine and this wasn't an issue some weeks back with the last project I created. Any assistance on this issue from anyone will be very helpful because I'm a quite a newbie to CubeIDE. Thanks.

I was trying to implement emulated EEPROM and I think I set the EEPROM page area right into the critical option bytes area. Notably, this didn't happen until I added the actual eeprom_emul.c and flash_interface.c files into the cmake configuration, compiled and flashed the program once. This obviously makes a call to "HAL_FLASH_UNLOCK()" so I think it's pretty messed up. Either way, after this, I could not flash the chip beyond 0x80000050, additionally, it would instantly lock up on boot. I believe my Option Bytes were also grenaded.  PCROP_RDP turned itself on, ESE turned itself on and the rest I am unsure of changes. Either way, I managed to turn off RCROP_RDP by setting RDP to 1 and then to 0. After this, flashing the chip, fills every line with the same repeating nonsense bytes. So I think write protection is disabled, but it's still uploading nonsesen. Notably, trying to hit "full chip erase" does not work, and just hangs. Now ESE remains checked. When try

Hi!I'm building a device using a STM32U31xx, connected to a Network Chip via I²C (PB6/7) and 2 GPIOs for Reset and BOOT0 Pin. The intention is to have new firmware downloaded onto the network chip, and flash new firmware to the STM32U031 via the system bootloader.I power up the system to invoke a power up reset on the ST device, I immediately flash firmware and ask the chip after another reset cycle for the new firmware version to confirm the new firmware was flashed.The behavior I observe is the following:- if the STs Option Byte nBOOTSEL is 0, the process works just fine, very reliably.- if nBOOTSEL is 1, the process fails even if I mass erased the STs flash memory entirelyThis is contrary to my understanding of AN2606 Table 2, pattern 11, that states that the empty check should start the system bootloader no matter the state of nBOOTSEL bit or BOOT0pin.I intended to have the ST chip flashed on production without previous intervention into th

Hello,I am writing this because I am unable to enable the SAI on this development board. The strange thing is that I actually managed to enable it before and it was working correctly. However, while implementing another feature, I switched branches and worked on a different GitHub branch for some time. When I came back, I noticed that the SAI was no longer starting.At first, I thought I had made a mistake in a commit, so I created a completely new project where the only goal was to start the SAI. Even though I believe all the steps are configured correctly, the MCK clock never starts, and the MCKEN register bit never becomes enabled. I am attaching screenshots of the SAI registers below.

Hi everyone,I have published a small bare-metal USB-C Power Delivery sink example for STM32 MCUs with the built-in UCPD peripheral:https://github.com/robobtnet/stm32-usb-pd-baremetal-sinkThe goal is to keep it minimal and portable:- no FreeRTOS- no ST USB-PD middleware- only two core files: pd_bm.c and pd_bm.h- configurable sink profiles- starts from the highest configured voltage profile, then falls back to lower profiles- reports the selected PD contract through the APIThe current tested setup is NUCLEO-G474RE using UCPD1. I also added porting notes for STM32U5/GPDMA based on an STM32U575 test project.I would appreciate tests and feedback on other STM32 families or boards that include UCPD, especially:- STM32G0- STM32G4- STM32U5- STM32L5- boards using UCPD2

Hi all,I'm looking for recommendations on eMMC chips that are known to work reliably with the STM32H743 via SDMMC1 in 8-bit mode.I've gone through a number of threads here and put together what I've found so far:- Micron 4GB (MTFC4GACAJCN) — comes up often, though some posts mention HAL misreading certain CSD fields (appears cosmetic rather than functional)- Kingston 4GB — confirmed working with SDMMC1 + FatFS + FreeRTOS, corruption reports seem tied to FatFS rather than the chip itself- Samsung KLM series — functional but VCCQ voltage negotiation adds complexity- Kioxia THGBMDG5D1LBAIL — 153-ball WFBGA, eMMC 5.0, fewer reports but looks promisingHappy to keep things simple — 3.3V on both VCC and VCCQ, no need for HS200/HS400.Would love to hear from anyone who has had long-term success with a particular chip, or any that are worth avoiding. Any layout tips for the 153-ball WFBGA package are also welcome.

I'm using an STM32H7S78-DK with TouchGFX and FreeRTOS. I would like to limit the framerate of the target to 30fps but withouth reducing the LTDC frequency.Basically having the VSYNC fired at 30fpsI've already set the  ((touchgfx::HALSDL2*)&hal)->setVsyncInterval(33.333);In the simulatorIs there a way to force it on the target?

Is there any utility in the holes and silkscreen circles around the TFBGA225 on the NUCLEO-H7S3L8?  It appears to be the same pattern on the Discovery board, suggesting it might be for BGA placement or maybe a heatsink. Edited to put the image in-line for better visibility

Hello Team,We are using the internal SMPS configuration for the core power supply. However, the power-up sequence does not specify the timing requirements for the different stages.Could you please provide the timing details for the following? What should be the time duration for the PWR_ON signal to transition from low to high while VDD and VDDA18AON are rising (Step 1)?After PWR_ON goes high, what is the required time duration for VDDA18PMU / VDDSMPS to rise (Step 2)?What is the exact meaning and function of the SDEN signal?Are there any additional considerations or recommended guidelines to be followed during the power-up and power-down sequence? 

Hi, hope you doing good,In our design, we are using the ST60A3H1C1CCEPY3 controller. please clarify if there are any layout restriction or keep-out zones around the controller where other peripherals should not be placed.Thanks,