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I am a user of the NUCLEO-N657X0-Q board.I would like to use Keil MDK RTX5 RTOS together with Root of Trust.My development environment is as follows:1> Development tool: Keil uVision V5.422> Example source: STM32Cube\Repository\STM32Cube_FW_N6_V1.2.0\Projects\NUCLEO-N657X0-Q\Applications\ROT\OEMuROT_Appli3> Development board: NUCLEO-N657X0-Q4> Manage Run-Time Environment Setting I have added the osKernelInitialize() function to the main function as shown below.int main(void) { #ifdef PRI

 #include <stdint.h> #if !defined(__SOFT_FP__) && defined(__ARM_FP) #warning "FPU is not initialized, but the project is compiling for an FPU. Please initialize the FPU before use." #endif int main(void) { /* Loop f

Hi everyone, We are encountering a XSPI Deadlock on our STM32H7S7-Discovery board (STM32H7S78-DK).To provide some context, our system is configured as follows: External FLASH: Connected to XSPI1. Swapped through XSPIM to port 2 and operates in memory mapped mode. MCE1 is activated across the entire address range using the AES-STREAM Cipher. External PSRAM: Connected to XSPI2. Swapped through XSPIM to port 1 and operates in memory mapped mode. MCE2 is activated across the entire address range using the NOEKEON-BLOCK Cipher. The issue occurs when running an LZO decompression algorithm. The algorithm reads compressed data from the PSRAM and writes the decompressed output back to the PSRAM, while the code is being executed on External FLASH. At some point during decompression, the core completely freezes, no HardFault or BusFault is triggered, and the debugger

Is there a prize for the most trivial post? Opened up a new Nucleo-L476RG board (finally worked my way through the 10+ boards I bought a number of years ago) - it comes in a cardboard box now, nice. The Leds (LD1, LD3) were so bright, I couldn't probe anywhere around the micro or connectors without squinting. So I replaced the resistors for these Leds (1K, 100?) with 22K, things are much more mellow now. Most people are using these boards indoors, the Leds only have to be bright enough for people to notice - not beaming out like the Eye of Sauron.  Anyway, something for you to think about. Meanwhile, there's a few annoying clouds outside I need to shout at....

Hello,I am a French engineering student working on a startup project as part of my MBA. We are developing an interactive musical box for children aged 3 to 7 years old.The core feature of the product relies on RFID detection: small figurines shaped like musical instruments are placed on a circular rotating tray (15 cm diameter). Each figurine has an RFID tag under its base. When a figurine is placed on the tray, the reader must detect it and trigger the corresponding audio track.Here are our technical constraints:- The reader will be fixed under the tray, at a very short vertical distance (1 to 2 cm at most)- The detection zone must cover the full surface of the tray, meaning a lateral radius of 7.5 cm- The tags will be in slow rotational movement- The reader must be connectable to a PC via USB for prototyping purposes, so we can retrieve detected tag UIDs in real time via a Python or JavaScript script- Budget constraint: under 100€

Hi, I'm new to yocto project, I'm trying to bitbake  core-image-minimal image in yocto in stm32mp157d-dk1(scarthgap) ,by editing the bblayers.conf and local.conf in image, its successfully build and flashed into SD card , but I'm trying to boot device then it failed. I found in bootfs sector there was no files in it. I tried to build with kirkstone branch and it worked well, and then I tried to bitbake with scarthgap again and again. I used Ubuntu 24.04 and Linux mint 22.03, but scarthgap branch had the same problems.I wanna know the reason. BIG THX.

I'm using the mp215 with ddr3l (x16) and an ISSI dram ic that is 8Gb (1 gigabyte) which means it's a dual rank configuration compared to a more typical half gigabyte. As far as im aware all 1GB ddr3 dram ic's are dual rank.In AN5723 6.1 Note it says "8 Gbit DDR3 defined by JEDEC is uncommon. Practically, DDR3L density is limited to 4 Gbits (max = 1 Gbyte in total). Single rank only is required. ".an5723 link As far as I understand it it says it's not possible. However this is an older AN and i think it's for the mp25 series only (im using the mp21).However in the ST Wiki "How to setup the DDR configuration" section 5 the exact opposite is implied. This whole section repeatedly describes a "concrete example" of swapping the swapping the mp215-dk's lp

Hi there, I have firmware that uses UART1 and UART2 of the STM32G4 series. Both are intended to run on interrupts, but as soon as any signal is received by the MCU, an error occurs, causing HAL_UART_AbortCpltCallback to be called. Therafter, the interrupt no longer works. Are there any known issues with the interrupt on these STMs? Based on previous forums, people were limited by stack size and prefetch. However, different to those cases, my code doesnt enter a hard fault, rather it just hits the function: HAL_UART_AbortCpltCallback.The error that comes up during debug starts here in the hal code:/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Configure Rx interrupt processing */

About EVSTSPIN32G4, I started the code generated by MotorControl Workbench 5. Y.3 normally.If you transplant the IIC configuration of the pre drive and enable PWM output, the VDS will report an error.After carefully reading the generated code, it is found that before PWM complementary output, the lower tube is opened for charging, and the output PWM pre drive or VDS protection is written. Is there a routine for STSPIN32G4 IIC to configure PWM output?

Hi,I'm using brand-new, unmodified st32mp257f-dk dev board.When using starter package (https://www.st.com/en/embedded-software/stm32mp2starter.html#get-software) flashed onto sdcard according to https://wiki.st.com/stm32mpu/wiki/How_to_populate_the_SD_card_with_dd_command, system boots-up fine, see 'downloaded_no_panic.log'. Version is openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11.When using image built on my own - distribution package  (openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11)  according to https://wiki.st.com/stm32mpu/wiki/STM32MPU_Distribution_Package,

Hi STM Forum,I'm integrating a custom QSPI display controller with TouchGFX and ThreadX. I need to convert the TouchGFX framebuffer into RGB666 (6 bits per color) for a custom display interface that runs over SPI/QSPI.Here is my IOC. As you can see, I currently have only the QSPI and the clock connected.

As the title says, the most recent 1.3.0 version of the extension breaks functionality of the debugger for the STM32G473CET3 MCU (and possibly others). By "breaks functionality", I mean that it does not even connect to the MCU anymore.

Hello!I attempted running a basic FreeRTOS example on a STM32F407VET6 board using CMSIS v2 following some tutorials, replacing systick for either TIM 6 or 7 as HAL Timebase as many tutorials suggest. The code only blinks and LED on the pre-generated task.I could never get the program to work and by pausing execution I noticed it went straight to the default handler infinite loop. After reading a few posts it seems that the CubeIDE still does not generate the appropriate timer IRQ Handler within the stm32xxxx_it.c file and has to be added manually, as suggested by @Curtis B. on the posts attached bellow. void TIM7_IRQHandler(void) { /* USER CODE BEGIN TIM7_IRQn 0 */ /* USER CODE END TIM7_IRQn 0 */ HAL_TIM_IRQHandler(&htim7); /* USER CODE BEGIN TIM7_IRQn 1 */ /* USER CODE END TIM7_IRQn 1 */ } Adding the IRQHandler fixes the i

Hello, I’m trying to use an X-NUCLEO-IHM03A1 board with a STM32F401RE Nucleo 64 board and a small NEMA 17 motor. My goal is just to learn how to drive steppers with the POWERSTEP01 for various projects and I just can’t make it work. I first tried to port the Ponoor library for arduino to STM32 by adapting and rewriting most of it but it didn’t work. I also tried to look at the ST Library from the X-CUBE-SPN3 software but it doesn’t seem to use the HAL so I haven’t been able to understand much of it. SPI is configured correctly, I’ve watched all the ST videos and read the entire datasheet but somehow I can’t make it work.I checked the entire ST Community forum, I also tried to find code on github or google but I can’t find a single usable piece of code written for STM32. Could anyone who has worked with this component post his C / C++ code. Even a valid SendParamet

Hello,I have designed a custom board with stm32wb55. I used the reference schematic and checked everything but I cannot program the board from my cubeide. I have tried different configuration settings in Cube IDE but always got "No device on target" error. I connecte SWDIO, SWCLK, GND and NRST pin to my stlink. These did not work so I tried different configurations with OpenOCD too but they also failed with these symptomsSymptoms (Multiple attempts with OpenOCD at 100 kHz):SWD-DP responds reliably: chip identified as Cortex-M4 r0p1Examination usually succeeds: shows correct breakpoint and watchpoint countsHalt always fails with "Fail reading CTRL/STAT register" → "Not halted"Roughly 1 in 4 attempts fail to even initialize, but when init succeeds, halt always failsManual NRST-to-GND-then-release tried, same resultAlready reflowed the WB55 once with gel flux, no c

Hi: My goal is to perform full-duplex I2S using the STM32F722RET6 part. To achieve this using the pins available on the package it looks like I need to use SAI2 (sub-block B) as the master/TX and SAI1 (sub-block A) as a slave/RX synchronized to SIA2.The configuration of SIA2 in CubeMX works fine.  However, when I attempt to configure the slave side (SAI1-A) the I2S option is greyed out (see below). Can anyone help me to debug this? Many thanks, Bruce.

Hello,For one of my project, my goal is to use PTP to synchronise multiple STM32H563 to one host.However, when configuring the ETH Device, I can only enable RMII, as the "RMII_PTP_SYNCHRO" is greyed out.I've read the pop up that tells me to enable TIM2 as a slave with trigger source "ETR1 through Remap", Channel 1 as "Input Capture direct mode from Remap". And both "remap capabilities" are set to "is connected to ETH_PPS".Is there something that I'm missing ?Best regards

We’re happy to announce that STM32CubeMX2 v1.0.1 has been released and is now available. This patch release includes updates and improvements aimed at enhancing the user experience and supporting your development workflow with STM32. What’s new: Supports installing multiple versions of STM32CubeMX2 side by side on the same PC. Supports a graphical uninstaller for easier removal, available on all three supported operating systems: Windows, macOS, and Linux. Prevents certain user files from being overwritten during Project Export. Improves the Pack Update feature for new packs with minor changes that previously did not work as expected. Includes several other bug fixes. Get it here: Download STM32CubeMX2 from the

Section 36.6.1, Bit 18 (ITAMP3E) indicates that LSE frequency monitoring can be enabled. It appears that the hardware automatically detects when the LSE frequency goes above or below the defined thresholds and sets the ITAMP3F flag in the TAMP_SR register when an LSE failure occurs. When the LSE fails, ITAMP3 is triggered, which asserts the tamp_erase signal, and the backup registers are then automatically erased?

Hello,I want to generate an arbitrary waveform by a timer using DMA. The waveform is using different pulse widths and also varying periods in multiples of 25µs.By reading AN4776 and HAL documentation I figured out it should be possible with HAL_TIM_DMABurst_MultiWriteStart() function. Unfortunately I don't get an output signal except after reset where a short pulse can be seen. I assume this pulse is due to port configuration during initialization. After that pulse, the signal stays high.My setup (CubeMX):Nucleo32-L432, core clock 80MHzUsed timer is Tim16Prescaler is set to 399 => 80 MHz / 400 = 5µs resolutionARR and CCR preload enabledARR and CCR set to 0 (initialized in source code)DMA enablednormal modememory to peripheralWord / Wordincrement address on memoryinterrupt enabledFor a first run I

Here is the config:mcu stm32h743iit6flash 4 lines 1 bank 32mb W25Q256JVsdram 32mb W9825G6KHhere is the flow 1 read image background from qspi 2 decode image with axi sram at  #define JPEG_WORKSPACE_BASE 0x24040000 // AXI SRAM (fast) #define JPEG_WORKSPACE_SIZE (256 * 1024) // 512KB (up from 256KB)3 copy buffer to external sdram4 dma2d copy and display image .   scenario1 is ok LIBJPEG_DecodeToBuffer((uint32_t)IMG_NEW6, IMG_NEW6_SIZE, (uint32_t*)DECODE_BUFFER1); uint32_t decode_time = HAL_GetTick() - start; printf("✅ JPEG decode: %lu ms\n", decode_time); // Test 3: Display the image start = HAL_GetTick(); //Display_ImageAt_Fast((uint32_t*)DECODE_BUFFER1, 1024, 600, 0, 0);

Hello,I am currently working on a simple USB Power Delivery test project using the STM32G071C8.The system has two USB Type-C ports.I need to detect PDO information and eMarker capabilities in order to determine the appropriate power delivery behavior. However, eMarker detection requires VDM-related functionality, and I could not find any relevant examples or documentation on the official website to continue development.The usbpd_vdm_user files generated by STM32CubeMX are essentially empty, and I could not find any useful reference information in either STM32CubeG0 v1.6.3 or X-CUBE-TCPP.Could you please provide any related example code, application notes, or documentation that demonstrates:VDM handlingDiscover Identity floweMarker cable detectionSOP'/cable communicationAny reference material would be greatly appreciated and would help me continue development.Thank

I tried multiple times to generate code on Arch Linux with CubeMX version 6.17.0 and Import in CubeIDE version 2.1.1. I made a video with process. And I don't know why this not working. I tried last and previos version of packages for STM32F0. And I don't know but CubeMX copied files very very slow.I choosed CubeIDE toolchain in CubeMX.

Hello. STM32H5I'm used to cache operations using memory barriers (ISB/DSB), but looking at a function like HAL_ICACHE_Invalidate() or HAL_DCACHE_Invalidate() I can't find any. Are memory barriers not needed with STM32 ICACHE/DCACHE?

I am using the STM32U575CGU3 MCU in my project, where I transmit data using two CAN frames on the bus. I have configured a CAN transmission cycle time of 250 ms in my software. However, on a few PCB assemblies, I am observing inconsistencies in the transmission cycle time. On few boards, the cycle time appears to fluctuate (e.g., around 0.5–0.6 ms deviation), while on other boards, it works well. Could you please help me understand what might be causing this variation across different PCBAs? Any guidance on potential root causes or debugging approaches would be highly appreciated.