STM32 MCUs Products

Hello St community !for now i'm trying to build a project based on the nucelo-N675-Q board. I'm trying to interface an STEVAL-66GYMAI1 camera and plot 2 frames values into the terminal . I'm building my project based on this repo https://github.com/supungamlath/STM32N6_Survivor_Detection . I made sure to copy the middlewares for my specific sensor but i'm finding that the camera camera never streaming a real data based on the debugging and getting an callback error on line 1 I'm attaching

Hi, Planning to use VFQFPN68 package. I am confused about the max core clock I can use. CubeMx shows 550MHz for every "Power Regulator Voltage Scale (0-3)".I remember reading VFQFPN68 has only DCDC solution so max core clock is 400MHz Can anyone explain please?Thanks,Tim 

Hi ST community,I’m working with an STM32H563 MCU and trying to use the pin labeled JTDO/TRACESWO as UART7_RX because the datasheet/alternate function table shows that this pin supports UART7_RX. However, UART transmission works correctly, but UART reception does not work when using this pin. If I switch to a different pin, both TX and RX function as expected.Here’s what I’ve checked so far:Configured the pin in STM32CubeMX as UART7_RX (alternate function mode)Verified UART7 peripheral initialization is correctChecked baud rate and UART settingsConfirmed hardware wiring:External TX connected to STM32 UART7_RXCommon GND connected

Hello, I've just received my custom PCB with an STM32H743VIT6 MCU. It has a Samsung eMMC connected to the SDMMC1 interface (MMC 8 Bits Wide Bus) : (I'll link the eMMC datasheet below.) I'm encountering some issues while initializing the device with the MX_SDMMC1_MMC_Init function. More particularly it seems to be stuck in the HAL_MMC_InitCard function, on this block :  /* Card initialization */ errorstate = MMC_InitCard(hmmc); if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->State = HAL_MMC_STATE_READY; hmmc

I have a question regarding an F407 wake-up error. I am using an F407ZGT and have connected the power switch to PA0 using a pull-down resistor. HAL_SuspendTick(); HAL_PWR_EnableWakeUpPin( PWR_WAKEUP_PIN1 ); __HAL_PWR_CLEAR_FLAG( PWR_FLAG_WU | PWR_FLAG_SB ); HAL_PWR_EnterSTANDBYMode(); I have been using this code successfully. However, after modifying the firmware and downloading it, or when downloading via the gang tool, the MCU fails to wake up via the wake-up input—though not always. Once this issue occurs on a board, the wake-up function permanently stops working, regardless of any operations performed. Is there any way to restore the wake-up function? Please help me!

This is in relation to post "Strange behavior with STM32G474QE pin PB4(Solved: Re: Strange behaviour with STM32G474QE pin PB4 - STMicroelectronics Community)" I'm facing the issue of PB4 going high for 27ms approx after MCU reset. My design is freezed, And this pin is connected to a relay which turns ON when this pin goes high. The relay turn on time is 7.5ms. Is there a solution in code initialization so that this pulse stays below 7.5ms. I'm attaching the waveform. 

Hi,On the stm32c5 nucleo board (NUCLEO-C5A3ZG) there is T1S OA PMD driver (not mounted?).  In the header file "stm32c593xx.h" exists a 10BASE-T1S control register "MAC10BT1SCR". But there is no documentation in the Reference Manual RM0522 Rev 1, and I can't find a way to enable T1S on MXcube2.Can anyone help me here? Is the T1S PDM really integrated in the C5 series?I would really like to experiment with 10Base T1S.RegardsPatrick

Hi, I need to use a 5V external clock for an stm32g473. The datasheet in table 39. High-speed external user clock characteristics says Vhsel is max Vdd, but Table 12. STM32G473xB/xC/xE pin definition says PF0 / OSC_IN is FT_a (five volt tolerant). Is it safe to use an external 5V clock ? Thx, 

Ok, this is perhaps esoteric, so maybe there is some research out there.   I am looking at STM32U3 or STM32C5, but the problem applies to pretty much all CM33 based ST MCUs.  The bus matrix implies a fast multiplexor for GPDMA (and SDMMC) to SRAM1. So unless dealing with burst transfers to SRAM (yes, SDMMC does that, and the GPDMA channels with the 32 byte FIFO could do that if the transfer is a multiple of 4 bytes), this fast multiplexor seems to save 1 clock reducing a beat to 2 clocks (if somebody has details for AHB vs. APB, that would be interesting). So to minimize latency and maximize bandwidth, DMA buffers (.dma section) should go into SRAM1.    So if DMA goes into SRAM1, then should not all the stacks go into SRAM2 ? I would assume burst DMA to/from SRAM1 would introduce some additional latency, especially in the way for ISR stacking / unstacking. Is this just overthinking this, or is that measurable ?  

I would like to connect a 12-bit ADC operating at 10MSps to the PSSI interface of the STM32N657 device.  There is some confusion as to the nature of the clock source. The reference manual indicates that this may be either an input or an output.  If configured as an output, what is the source of the clock?  Examples suggest that a PWM timer needs to be used.  Here is an illustration of what I would like to do:Do I need to use the PWM timer as the clock source?

I'm using LPTIM1 in encoder mode and have noticed that, if there's jitter on one of the encoder signals the count will gradually creep up which should not be possible in encoder mode.This is on a decent encoder that's got an RC network (per the Bourns data sheet / appnote) in front of it too so this isn't nasty HF noise, it's good solid pulses of 50-100ms or more on one channel but the counter seems to creep up.Identical encoders wired to TIM2 / TIM3 behave normally, and my colleague has seen the same issue in another project using the same setup - LPTIM has a problem where TIMx does not.Init code for LPTIM1:/* LPTIM1 init function */ void MX_LPTIM1_Init(void) { /* USER CODE BEGIN LPTIM1_Init 0 */ /* USER CODE END LPTIM1_Init 0 */ LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); /* Peripheral clock enable */ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LP

I started getting this message when I try to debug my code. However, there are currently no breakpoints in my code at all. I have gotten this in the past and I deleted and redownloaded the IDE which I really do not want to do again. I am running it on Mac. Any suggestions are helpful.// Simple ADC Reader // ADC1_1 on PA1 // Port A on AHB1 // ADC on APB2   #include "stm32f4xx.h" #include "printUSART.h"   int val = 0;   int main(void){   USART2_Init();   RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;   GPIOA->MODER = GPIO_MODER_MODE0_0 | GPIO_MODER_MODE0_1;   RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;   ADC1->CR2 = 0;   ADC1->SQR3 |= ADC_SQR3_SQ1_0;   ADC1->CR2 |= ADC_CR2_ADON;   while(1){ ADC1->CR2 |= ADC_CR2_SWSTART; while(!(ADC1->SR & ADC_SR_EOC)){} val = ADC1->DR; printf("\n%d", val);   }   }

Hiya. I'm having some trouble understanding how an STM32 MCU communicates with an image sensor via DCMI if they operate on different voltages.My STM32U5Gxxx operates on 3V3, whereas my selected image sensor has its VDDIO at 2V8 (max input of 3V1). How can I make sure that all the signals I send to the sensor are at 2V8 instead of 3V3? Is there a certain VDDIOx pin to be tied?Are there any reference designs or schematics that are helpful?

As addicated in DataSheet and CubeMX, there are two FDCAN1_Tx and two FDCAN1_RX in STM32G431CBT6. In my Prj, I used PA12 for Tx and PB8-BOOT0 for Rx, and my chip can only work in FDCAN_MODE_Ext._Loopback, and without any receive func be implemented. After I changed the FDCAN pin from PA12&PB8 to PB9&PB8 and adjusted my wire routing, the problem has be handled. so If the STM32G4 can use FDCAN pin from different port in some case? If not. I think it should be fixed in CubeMX, because CubeMX allows users to select CAN pin from different ports without any warning.​

How to configure the sysTick_Handler(), when we are setting the HCLK 386MHz in CubeMX and systemClock() is generated, but while configuring sysTick(), uint32_t SystemCoreClock = 64000000; already there in system_stm32h7xx_dualcore_boot_cm7_cm4.c(void)SysTick_Config((SystemCoreClock) / 10000);Will it effect mine overall MCU speed and performance, because after all I'm using FMC NAND Flash to communicate with the external Micron Flash, because there I need to calculate the clock cycles need to the write enable (WE), Setup time, Address Latch Enable (ALE) time etc, will be effected, or it is completely independent, should I only consider FMC_CLK which is coming from PLL clock source 2.

Hi,  I'm using a STM32F072's DAC to output a SIN and a COS wave. The problem is I can only output values up to approx. VDDA / 2. The DAC drives unity gain amplifiers to drive a 50 Ohm load. The DAC is connected directly to the amps, using the buffer does not help. VDDA = 3.3 V. Here, CH4 is connected directly to the DAC output via a 10:1 probe. The black things on the scope inputs are 50 Ohm termination, so the CH2 and CH3 signals having only half the amplitude of CH4 is expected. All channels are DC coupled. I'm writing to the DAC using the DHR12L1/2 registers (using the STM32Cube HAL): 

Hello,Can anyone tell me how to measure pulse width with the HRTIM? I need to measure a very short pulse from my time domain reflectometer. I am thinking of using the NUCLEO-H753ZI board with the STM32H753ZI MCU. All I know about measuring pulses with the HRTIM is that I need to use the external event registers and that the minimum pulse width must be >2.5 ns. Any help would be greatly appreciated.

We need further clarification regarding the difference between the above ICs.We recently purchased the mentioned STM32 MCU, but received two different variants. In one IC, the ST logo on the right side has the marking “e3” with “L” outside the circle. In the other IC, the ST logo on the right side has the marking “e4” with “L” outside the circle.Kindly clarify the difference between the “e3” and “e4” markings and confirm whether both ICs are equivalent in specification and performance.

I am developing a device that implements the USB device class.According to application note AN4879 "Introduction to USB Hardware and PCB Design Considerations Using STM32 Microcontrollers" it is written as follows:Based on the USB specification, a USB device must use VBUS sensing detection. When the device detects the host presence, it connects its pull-up resistor to either a D+ or D- data signal. This allows the host to detect the device presence on the bus. There are two cases: • The USB device is bus-powered. VBUS sensing is not mandatory (USB is always connected when the device is powered)• The device is self-powered. VBUS sensing is mandatory. Pin PA9, a five volt-tolerant pin, which includes an additional function natively dedicated to VBUS sensing. I have an option when the device is self-powered. Therefore, VBUS sensing is mandatory.It is also written

I got another strange issue with a STM32F3, as usual related to DMA.The problem relates to an "old" DAC / DMA example I tried to port to a different MCU.The original is called "DMA_RAM_DAC", and is part of the V1.1.0 firmware package for the F303 discovery board.(.../STM32F3-Discovery_FW_V1.1.0/Project/Peripheral_Examples/DMA_RAM_DAC)Building and running it on this target, it works fine.However, my actual target hardware is the F3 Nucleo32. This board has a STM32F303K8T, instead of the 'huge'  STM32F303VCT on the F3-Discovery.The relevant difference here is, the mentioned example uses DMA2 channel3, which does not exist on smaller devices like the STM32F303K8. According to the reference manual, the relevant DMA request can be mapped to DMA1, by setting corresponding bits in SYSCFG (RM0316 Rev.10, page 267, 269).To do this DMA request mapping, bit 13 in SYSCFG->CFGR1 needs to be set.And here is were the problem starts.N

I'm using the LCD of the STM32U073K8, but the program failed to initialize the LCD. After checking, I found that the STM32U073K8 doesn't have the VLCD pin. Is the STM32U073K8 not compatible with the LCD peripheral? Or are there other settings?

Hi All,I've this requirement, can someone suggest how do I proceed.I'm using stm32u535 and over usart it's connected to Silicon labs chip. Silicon labs chip has Wi-Fi and I want to update firmware of STM32U535. This silicon labs chip is connected to cloud over Wi-Fi. 

We are currently working with a custom PCB using an STM32N6 chip and an MX25UM512G flash chip. The flash is connected identically to the Nucleo development board.When powering up the board in Dev Boot mode, it is not possible to read the flash chip using CubeProgrammer. The MCU crashes, which we assume based on the reduced power consumption observed afterward.If we first load a firmware image into SRAM using CubeIDE (which successfully connects to and reads the flash memory), then reading and writing the flash via CubeProgrammer works as expected.However, after a power cycle without reloading the firmware into SRAM, the flash becomes inaccessible again.Additionally, after flashing the firmware using this workaround (i.e., initializing the flash via our own firmware and then booting in Flash mode), the software is not executed from flash and the system does not boot.Our assumption is that the flash is not correctly initialized by the boot ROM. Any h

Hello everyone. I am running into a USB Host <--> Device connectivity issue. I have 2 STM32L496 MCUs, one as Host and other as Device. I cannot get the CDC connectivity to work for some reason. The connections are as follows: D+ <> D+, D- <>D-, GND<>GND.I have VBUS, SOF and NOE disabled. CubeMX forces to set Drive_VBUS as well over a GPIO, however, I am not using that in my circuit. Even though it is a recommendation in USB connectivity in AN4879, I believe it is possible for a simple connectivity without it as well. Would this be a wrong assumption (and hence the culprit)? As a connection stability, I tested both MCUs individually as Devices, connecting to my PC and it sent data over USB just fine. The attached code has NucleoL496 as the host. Would appreciate your support.

Hi,   I am implementing a Dual Active Bridge (DAB) DC-DC converter on an STM32L476RG Nucleo board. The goal is to generate 8 complementary PWM signals using TIM1 (Bridge 1) and TIM8 (Bridge 2), both at 5 kHz with 50% duty cycle, and to control the power transfer by adjusting the phase shift between the two timers.   The phase shift must be adjustable at runtime (via button, potentiometer, or PID controller) without affecting the 50% duty cycle.   I tried three synchronization approaches, all of which failed:   1. Reset Mode (SMS=100): TIM1 sends a TRGO at the end of each period. TIM8 receives it and resets CNT to 0, which cancels any preloaded phase offset every 200 µs. The phase shift cannot be maintained.   2. Trigger Mode (SMS=110): TIM8 starts on the first TRGO then runs freely. The initial phase is correct but there is no ongoing synchronization, which could cause drift over time.