STM32 MCUs Products

As I understand, the TSSOP20 version needs an external oscillator instead of a 8MHz crystal connected directly to the MCU pins. Is that correct?I'm asking because I have seen a board on AliExpress using this same processor with a 8MHz crystal.

Hi, I have bought STM32H743VGT6 and want to make bootloader and application. The issue is that its memory layout is confusing. In documentation and generated application I see/assume flash memory is:0x8000000 size 0x80000 (512kb bank1?) // bootloader 0x8100000 size 0x80000 (512kb bank2?) // applicationBut when I try to write to 0x8100000 I get "Error occured during memory writing!". Instead I can write to0x8000000 size 0x100000 (1024kb)Does this mean I have only Bank1, but no Bank2? Can I still do bootloader which is on Bank1 and writes to flash on same Bank in different sector? How can it be that I have only one Bank?..

Hi,I already tried to search for previous threads that could help me (like this one), sadly without success.I'm currently studying the ADC peripheral on STM32F3DISCOVERY from the reference manual. I started writing a simple program to measure a tension on PA0. It all works flawlessly until the ADC samples the value on PA0, stores it in the Data Register and raises EOC. From the manual:"The ADC sets the EOC flag as soon as a new regular conversion data is available in theADCx_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared bythe software either by writing 1 to it or by reading ADCx_DR." (page 347, Section 15.3.23).The loop part of my code is the following (I already configured the ADC for single conversion mode, L[3:0] = 0

Hello Everyone,During the operation of my program, there will be an issue of address inversion on stm32f030c8.It occurs approximately every 4 hours, and then it transitions to a "hard fault".For example, I was trying to read from address 0x20000940, the register R0 returns 0x20400940, 1 bit was flipped, and it is out of the range of ram address(0x20000000-0x20002000), runs into hardfault in the end.I measured the surface temperature of the chip, and when the problem occurred, the surface temperature of the chip was 65 degrees.I suspect it's a problem caused by excessive temperature, so I used a fan to blow on it. It has been running for a whole day and is still functioning normally.The vcc of the MCU is 3.3V. I used external crystal oscillator 8M, the PLL  Clock is 48MHZ, configuration like follow:    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;/** 使用外部晶振（8mhz） */    RCC_OscInitStruct.

G4 ref man says there is 1 (one) FDCAN peripheral:Yet when editing the IOC file I see 2 (two) FDCAN peripherals:I believe the ref man. What's with the IOC file editor?

Hi All,  In my application, I am using the STM32L451RCT6 and trying to configure COMP2 with the internal Vref as a reference (specifically 3/4 Vref). For some reason, it never worked. I was only able to get it working when using DAC_CH1 or an external source as the reference. After a few days of troubleshooting and research, I finally found a relevant block diagram along with an important note in the reference manual (page 532). The thing is, there are no mentions or explanations of this behavior in the reference manual, datasheet, or errata other than this. Could you confirm whether

Hello, Can someone pls help me fill this information out for STM32H753VIH6? Thank you.      Model NameCheck Group１ (注１)２ (注２)３ (注３)４ (注５)Ministerial Ordinance Article Number第６条第一号イ第６条第一号ロ第６条第一号ハCheck ItemsPresence or Absence of Radiation-Hardened DesignDesign IntentRated Operating Temperature Range (°C) Whether or not compound semiconductors are used (Note 4)Maximum Clock Frequency (Note 4) (MHz)

Hello,   ich set up my project with CubeMX for a CAN-FD (1 MBit/s / 4,8 MBit/s) and a Display for communication. Now i have the problem, that the SCK Signal for the communication looks more like a sawtooth signal than a rectangle. Also the SPI-Prescaler for the baud rate does not affect this signal. i am really confused. I need to use the 48 MHz HSE for my 4,8 MBit/s data phase for CAN-FD. I use an NUCLEO-C092RC and a LCD Display with ILI9341 (library from Mauro De Vecchi) Thanks for the help

Hello. Please check if there are any issues with the settings as shown below. PB4 : SPI1_miso PB3 : SPI1_sck PD6 : SPI1_mosi   Thank you.

MCU : STM32WLE5CCU6Firmware Package Name and Version : STM32Cube FW_WL V1.4.0Application : FUOTA using LoRaWANSetup : End Node(STM32WL) <===> Gateway(Dragino LPS8) <====> TTNHello, I am trying to get my LoRaWAN FUOTA example running for few days with unsuccessful attempts.At first i was successfully able to build LoRaWAN FUOTA application provided by ST under STM32Cube_FW_WL_V1.4.0. This firmware is made for NUCLEO-WL55JC(STM32WL55JC, Dual core with 256KB flash)But as i have STM32WLE5CCU6(Single core 256KB flash). With that also i tried to change the startup and linkers and updating .cproject with correct part number and was able to build it but while flashing gets an error.\STM32Cube\Repository\STM32Cube_FW_WL_V1.4.0\Projects\NUCLEO-WL55JC\Applications\LoRaWAN_FUOTA\Scripts\STM32CubeIDE> .\program.bat

Hello,I have a custom board based on the STM32U5A5 microcontroller. I am trying to run a fingerprint reader sensor over USB on this board. For this project, I am using USBX Azure RTOS.The configurations I made on the CubeMX side are as follows:High Speed Clock: Crystal/Ceramic ResonatorLPUART1 for UART communication:Mode: AsynchronousBaudrate: 115200 Bits/sPB10 -> LPUART1_RXPB11 -> LPUART1_TXUSB_OTG_HS Mode and Configuration:Internal HS PHY -> Host OnlyPA11 -> USB_OTG_HS_DMPA12 -> USB_OTG_HS_DPActive_VBUS -> DisableNVIC Settings -> USB OTG HS Global Interrupt: EnabledPA9 GPIO Output enabled for USB power (I verified that the device is powered correctly.)THREADX Mode and Configuration:Core: Enabled

There seems to be a documentation error between DS14053 Rev 4 and RM0492 Rev 3.  In the data sheet, section 3.17, table 3, "ADC Features" we see a different set of features compared to the reference manual, section 19.3, table 107.  The data sheet claims oversampling up to x1024, a data register of 32 bits and gain compensation is supported.  The reference manual claims oversampling up to x256, a data register of 16 bits and no gain compensation.The register set description only has oversampling fields with values up to 256.  It would be helpful if ST could correct whichever document is wrong, and if the reference manual is wrong and oversampling up to x1024 is supported, then please also correct the register definitions.Thanks,TG

STM32H743VGT6 how to use slave I2C+DMACurrently, this usage is fine. However, when using the DMA function, it will trigger an ER interrupt.HAL_I2C_Slave_Seq_Receive_DMA, How to use it? Are there any examples?// 从机地址匹配回调函数 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) { if (hi2c->Instance == I2C1) { if (TransferDirection == I2C_DIRECTION_TRANSMIT) { Rx_len = 0; memset(I2C_rxBuffer,0,4); HAL_I2C_Slave_Seq_Receive_IT(&hi2c1, I2C_rxBuffer, 1, I2C_FIRST_AND_LAST_FRAME); } else { HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, I2C_txBuffer, Tx_len, I2C_FIRST_AND_LAST_FRAME); } } } 

Hi, I'm using the STM32C071K8U6's built-in USB DFU bootloader for one-time production programming. After flashing, PA11/PA12 (USB D+/D-) are used as regular GPIO outputs to control two P-MOSFETs (each with their 100kΩ gate pull-ups to 4.2V).   The USB functionality is not used by the end customer, but the USB connector remains accessible for charging. This means a PC's USB cable may be connected during normal use allowing for potential signal injected into those traces resulting into the PMOS being turned on/off by the PC if it detects there is a USB device connected and tries to enumerate it.   The two core issues: a) When a user plugs into a PC for charging, we need to guarantee the host does not attempt enumeration, and that nothing the host does on D+/D- interferes with our GPIO-driven MOSFET gates. b) because the&nb

Hello,I would like to ask about the UFQFPN32 package footprint for the STM32G491KEUx device.We are using the following part:Part number: STM32G491KEUxPackage: UFQFPN32While reviewing the datasheet and package information, we found that the actual UFQFPN32 package appears to have an exposed pad (EP) on the bottom side of the package.However, in the datasheet/package information we reviewed, the UFQFPN32 package information and footprint example do not seem to include the EP or the EP land pattern.In particular, the UFQFPN32 package information is shown in the document from page 166 to page 168, but we could not find any information regarding the exposed pad or the recommended PCB land pattern for the EP.Could you please confirm the following?

Dear STM Engineer, thank You very much for Your great effort  for the new STM32V8. My comments on the features after looking into stm32v8-presentation.pdf: - STM32V8 will have a ETH-Gb-MAC with PTP, that is great news for applications in the field of scientific instrumentation. -- I am missing PTP-Timestamp-capture-peripherals to generate PTP-precise timestamp input-pulse captures on external events. So triggered by one GPIO input-pulse-edges  (or better several logic-combined GPIOs, at least two to have one "gating), a timestamp (64 Bit or more?) should be stored, including in its timestamp-word at least two (better four or more) GPIO Input-states: state high/low AND edge falling/rising. We would need as many as possible of these PTP-Timestamp-capture-peripherals as possible, e.x. 16 or more of them per MC. Would You consider to include such PTP-Timestamp-capture-peripherals into STM32V8? - -  I am missing PTP-ou

ST moderator: post split from this thread. Hello mƎALLEm, Thank you for your confirmation on this issue. I would like to provide some additional information. I have also encountered the same problem on the STM32F405RGT6. In STM32CubeMX, when I configure both HSE or LSE to "Bypass Clock Source" mode, the tool insists on reserving PH1 (OSC_OUT) or PC15 (OSC32_OUT) as RCC pins. It blocks me from configuring them as regular GPIOs, even though the hardware (as you've confirmed) supports it.

Hi, We are planning to use STM32H743ZI for our project. Our requirement is to interface a 7-inch LCD touch display with 1024x600 resolution using a 24-bit RGB interface (RGB888) through LTDC. Can STM32H743ZI reliably support this display resolution? Also, what frame rate can realistically be achieved with this configuration? Are there any important hardware or performance considerations before selecting this MCU? Any suggestions or reference designs would be helpful. Thanks.

Hi all, I'm planning to use USB (DFU mode) for production programming of the STM32C071K8U6 — including the very first firmware upload. The board has no external crystal; I intend to rely solely on the internal RC oscillator.   A few questions: 1) Is USB DFU feasible on this specific part without an external crystal? I've read that not all STM32 variants support USB boot without an external crystal (due to clock accuracy requirements for USB). Can anyone confirm whether the STM32C071K8U6's internal oscillator is sufficiently accurate for this?   2) Are there any specific hardware or configuration requirements I should be aware of for first-time USB DFU programming on this part? As the moment I just have the two USB traces connected to the USB connector but no 5V (VBUS) connected anywhere to the micro. I also have a pushbutton on the BOOT

Hi, we have purchased stm32h750vbt6 microcontroller for analog signal validation with 10k potentiometers to integrate with game controller joystick especially joy.cpl using windows 10 OS.   We have dealt with DMA Circular mode configuration pointing cortex-M7 DRAM to 0x30000000 to retrieve the analog signals associated with respective 10k potentiometers. Totally we have four analog pins such as PA0,PC0,PA3 and PC5 from ADC1 & ADC2 with proper distinguished rank allocation alongside desired maximum sampling cycles but although we have altered and tested with different values of this above configuration it ended up with ADC channel leakage which is declared 16 bit ADC.    Moreover we have tried adding external 100nf capacitors to avoid these linkage but failed.    We kindly request you to resolve the ADC channel leakage in our current stm32 Project. Our entire stm32 project attached for your reference and fault ide

is there a way to search for which stm32h7 mcus have integrated HS usb phy?the mcu finder product selector doesn't have such filter, is there an app note, a product brief or anything like that?How is one supposed to find such a controller? (besides manually checking all of them)Sometimes this is the main and only selection criteria. I didn't even know that such a feature even exists.I just stumbled uppon when i saw that the stmlink v3 has high speed usb but doesn't use an external usb phy. 

DeviceSTM32H563ZIT6, single binary (no separate bootloader), dual-bank OTASetup Bank1: Current running firmware (original)Bank2: New OTA firmware (potentially corrupted)IWDG: Started in Bank1 before swapOTABootSafetyCheck: In Reset_Handler of every binary buildBKP0R: Boot counter set before swapProblemAfter bank swap, if Bank2 firmware is corrupted and Reset_Handler never executes:  Bank swap → resetCPU reads 0x08000000 → SP (may be valid)CPU reads 0x0800000

Hello,I am designing a high-speed data logging architecture using STM32H743VIHx. I would like the community to validate my DMA architecture and answer specific questions about eMMC access. I did not find answers in the forum and I am also not an expert in microcontroller hardware/software architecture. --- SYSTEM OVERVIEW ---The logging produces a continuous signal sampled by the ADC. I need to log raw data samples along with GPS and IMU data to an eMMC for post-processing.Key parameters:- ADC: 14-bit dual interleaved on PA6 (ADC12_INP3), differential ~10 MSPS effective- eMMC: S32 GB, eMMC 5.1- SDMMC1 in 8-bit MMC mode- IMU: on SPI2 (PB12-15) at 8 kHz- GPS: on UART4 at 115200 baud --- PROPOSED DMA ARCHITECTURE ---Four concurrent DMA paths:1. ADC1+ADC2 interleaved → DMA1_Stream0 → AXI SRAM (ping buffer)Triggered by ADC1 EOC, reads CDR register (32-bit = 2 interleaved samples)

Hi, I have all configured using internal loop FDCAN1 and there is not working on my STM32G474RE-Nucleo board 

Hi, We are busy making a setup with 2 nucleo-c092rc boards. Our first test was to send from board 1 to board 2 by the integrated CAN interface on these boards. We started at 1Mbits and this worked great. Also on 4Mbits the setup worked great. But we also want to test this on 8Mbits and now the transmitter is not sending correctly. We only see that the arbitration phase is send out and a couple of bits of the data part, but then the transmitters stops sending. We have tried with internal HSI(48Mhz) and external HSE crystal which is also 48Mhz on the nucleo boards.  We calculated the values for the SyncJumpWidth and timeseg1 and 2 and also tested with values slightly altered. hfdcan1.Init.DataPrescaler = 1; hfdcan1.Init.DataSyncJumpWidth = 2; hfdcan1.Init.DataTimeSeg1 = 2; hfdcan1.Init.DataTimeSeg2 = 3; But we allways have the same outcome. Sometimes it's not sending anyth