STM32 MCUs

Hello ST community, I configured my project in STM32CubeMX 6.17.0 and use STM32CubeIDE 2.1.1 to debug. The goal of the program is to receive a raw ethernet frame.I followed this tutorial, of course I adapted the pins to NUCLEO-N657X0-Q, and I skipped the part with the transmission, I didn't change anything in the HAL_ETH functions. I am sending from the PC (I can see that the frame is sended with wireshark):from scapy.layers.l2 import Ether from scapy.packet import Raw from scapy.sendrecv import sendp #Terminal ipconfig /all dst_mac = "00:80:E1:00:00:00" src_mac = "AA:79:39:37:92:EA" payload = bytes([0x01] * 86)

Hello,I am working with an STM32F103RB Nucleo board. I am able to successfully connect and program the device using ST-LINK, but I am facing an issue during debugging.The code is downloaded successfully and verified, but when the debugger tries to run (after the 'cont' command), it fails with the following error:Error in executing 'cont' commandTarget is not respondingFailed to read all registers from targetSetup details:- Board: NUCLEO-F103RB- ST-LINK Firmware: V2J47M34- STM32CubeProgrammer: v2.20.0- Debug Interface: SWD- Connection Mode: Under Reset- Reset Mode: Hardware reset- SWD Frequency: 125 kHzObservations:- Programming completes successfully- Verification is successful- Issue occurs only when starting execution/debuggingThings I would like help with:1. What could cause the target to stop responding immediately after programming?2. Could this be relat

Hello Peter ,  Need your expert reply  As we see , the confusion on N AND no N HAS MADE many of us wonder , if these can be used as  interchangeable parts . Since Data Sheet does not explain , much on them ,But a search explains a compact Solution in Io's for a design flexibility .  As both have same Packages and Pin  Count .  We are in need for DESIGN - STM32G0B1CBT3N , but seems to be difficult  to procure  . Is this Manufactured or is it rare . We only See STM32G0B1CBT6N    Regards Nitin

Hi,After reading HSO current and voltage sampling in three-shunt topology, I beleve it is possible to run two BLDC moters using the ST-G473 microprocessor using 2 ADC's per motor. However, there does not seem to be support for that in the MC Workbanch. Will this be available in the future?Regards, Kevin

hello ST Community, I need your support. So far, I've been able to flash my bootloader software into the unprotected memory area 0x08000000 when Boot0 = 0 for the NUCLEO-H755ZI-Q series, both with the STM32CubeProgrammer and with my bootloader software via UART. However, I'd like to flash the same bootloader software into the memory area 0x1ff00000 when Boot0 = 1. I know it's protected. Is it possible to change the security level or flash it to another memory to run my software when Boot0 = 1? Thank you for your support.

Only 2 of 4 QSPI data lines active during pixel write, despite DMODE=3 confirmed in CCR   이미지 4장을 모두 참조하여 ST Community 문의 글을 작성합니다. Environment MCU: STM32U5G9ZJ (Cortex-M33, TrustZone enabled) IDE: STM32CubeIDE HAL version: STM32U5xx HAL Driver (included in project) Interface: HSPI1 → QSPI LCD (ICNA3306-compatible controller)   Hardware Configuration GPIO settings are shown in [XSPI_2.png]. All six HSPI1 pins are configured as Alternate Function Push-Pull with GPIO_SPEED_FREQ_VERY_HIGH and GPIO_AF8_HSPI1: Pin Signal Speed PI3 HSPI1_CLK Very High PH9 HSPI1_NCS Very High PH10 HSPI1_IO0 Very High PH11 HSPI1_IO1 Very High PH12 HS

Is it possible to connect 8 PDM microphones to the STM32N6 via MDF?

Hello,I am facing an issue with the STM32C5 HAL SPI driver related to CRC error detection.In my setup, CRC is enabled for SPI. When a CRC error occurs, I can observe that the CRCERR flag is set before the transfer is closed. However, the CRC error is never reported via the HAL error callback.Looking into the HAL implementation, I noticed the following behavior:SPI_CloseTransfer() calls LL_SPI_Disable()After disabling SPI, SPI_CloseTransfer() checks LL_SPI_IsActiveFlag_CRCERR()When this check is performed after LL_SPI_Disable(), the CRC error is no longer detectedIf I move the LL_SPI_IsActiveFlag_CRCERR() check before LL_SPI_Disable(), the CRC error is detected correctlyAdditionally, in my case SPI_CloseTransfer() is called from HAL_SPI_IRQHandler(), but:the return value of SPI_CloseTransfer() is not evaluatedonly the Tx/Rx complete callback is invokedmy error callback

This is an improvement request post.STM32 HAL on every family has tons of following code constructs:tickstart = HAL_GetTick(); while (!condition) { if ((HAL_GetTick() - tickstart) > TIMEOUT_VALUE) { return HAL_TIMEOUT; } }When using HAL with (Free)RTOS or interrupt based scheduler, then these while loops delay same priority tasks (until time-slicing kicks in), block everything that has lower preemption priority, waste energy (crucial for battery powered devices) and decrease responsiveness.There are multiple ways to improve it. One of the simplest is to supplement non-critical* loops with optional user-definable yield macros.__weak void HAL_Yield(void) { } tickstart = HAL_GetTick(); while (!condition) { if ((HAL_GetTick() - tickstart) > TIMEOUT_VALUE) { return HAL_TIMEOUT; } HAL_Yield(); }Now user can im

Hello, I have a STM32 NUCLEO-N657X0-Q development board. I wanted to interface with 8 digital PDM MEMs microphones.  In section 68.2 of the STM32N6 reference manual, it states that the N6 supports a "PDM interface, supporting up to 4 microphone pairs". Also in section 2.2.3 of AN5027, it states that if 8 microphone want to be used, the recommended data IO lines are SAI_D1, SAI_D2, SAI_D3, and SAI_D4. Using CubeMX, I see no option for microphone pair 7-8. In addition to this, SAI_D4 doesn't exist when I search for the pin.  So how do I interface (if possible), the last microphone pair?  Thanks, Christopher

Hi everyone, I am currently developing an image capture project using the STM32N657 (Cortex-M55) and have encountered an extremely bizarre DMA2D write issue (a silent failure). Goal: Use DMA2D (M2M_PFC) to convert an RGB565 buffer to RGB888 and write it to CPUAXI_RAM1 (0x34080000). [Problem Description] I wrote a "minimal isolation test" to bypass all camera/GPDMA variables. I forced the CPU to fill the source buffer with pure white (0xFFFFFFFF), and then manually triggered the DMA2D to transfer it to the destination buffer. The Result: The DMA2D finishes successfully. The DMA2D->ISR register reads 0x00000002 (the TCIF Transfer Complete Interrupt Flag is set, and there are NO Transfer Errors). However, the destination buffer remains completely filled with 0x00000000. [Troubleshooting Done] To isolate the issue, I have verified the following, but t

Hello, I am working with the following setup: Board: B-L4S5I-IOT-01A MCU: STM32L4S5VIT6 BLE Module: BlueNRG-M0+ (in built in the Kit) I am currently facing an issue related to the BLE MTU (Maximum Transmission Unit) size. By default, the payload length is limited to 20 bytes, which is insufficient for my application, as my data length exceeds 180 bytes. I would like to know: Is there a way to increase the MTU size on the BlueNRG-M0+? Can this be achieved without modifying my existing data transmission mechanism (i.e., without manually fragmenting the data into smaller packets)? My goal is to transmit larger data packets in a single operation, if supported. Any guidance or recommended approach would be highly appreciated. Thank you.

Title edited to clarify this is about CMSIS-RTOSHello, everybody!I don't know where to look for information on which CMSIS versions are supported by specific STM32 microcontrollers. I asked one of the ST employees and STM32 Sidekick about this, and I got no definitive answers.STM software tools confuse me further. For example, STM32CubeMX (6.17.0) allows me to choose CMSISv2 the interface for FreeRTOS in my STM32F769I‑DISCO board project, but LwIP in the same project does not see the operating system used unless I change the CMSIS version to v1 (you can find more details about this specific issue in this thread). I couldn't find any document that would say which interfaces are supported by LwIP either.That's why I would like to ask You, where should I look for informat

Hello Team, We are using STM32N657X0H3Q for one of our application, while looking for the voltage level information for pins, we did not get any information for PA0 pin for the controller, specifically i am referring the notes column in pin description section. I hope you are getting my question.  RegardsHarsh Bhavsar 

My USB ECM project on NUCLEO-U575 and NUCLEO-U5A5 - it works now, on all OS platforms.https://github.com/tjaekel/STM32U5xx_USB_ECM This project and demo for a STM32U575I-EV (where I have converted from) needs a vendor driver on Windows.Windows does not support USB ECM (or USBLAN, just RNDIS, but it is different). There is not any driver to use USB ECM on Windows, except: Belcarra USBLAN demo driver.Dear STM Team:please, could you consider to license the Belcarra USBLAN driver for Windows?http://usblan.belcarra.com    

I configured a nucleato-L152RE LED program using CubeMX6.17+STM32L1 Firmware Package V1.10.6 and found that the program kept restarting automatically. After adding the following code to the SystemInit() function generated by CubeMX, the problem was solved. What is the reason for this? And my other projects never need to include this line of code, such as F103, F411, G431, L051, and so on.SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET;

Hi I'm using STM32F411RET6 MCU. I tried to connect using the programmer to download the firmware, but there was an error as shown below, and the data cannot be read. 13:18:34 : UR connection mode is defined with the HWrst reset mode13:18:34 : ST-LINK SN : 54FF7106788056521117016713:18:34 : ST-LINK FW : V2J45S713:18:34 : Board : --13:18:34 : Voltage : 3.22V13:18:34 : SWD freq : 4000 KHz13:18:34 : Connect mode: Normal13:18:34 : Reset mode : Software reset13:18:34 : Device ID : 0x43113:18:34 : Revision ID : Rev A13:18:34 : Debug in Low Power mode is not supported for this device.13:18:34 : UPLOADING OPTION BYTES DATA ...13:18:34 : Bank : 0x0013:18:34 : Address : 0x40023c1413:18:34 : Size : 8 Bytes13:18:34 : UPLOADING ...13:18:34 : Size : 1024 Bytes13:18:34 : Address : 0x800000013:18:34 : Read progress:13:18:34 : Error

Hi, I am using STM32U385CGU6 with 1.8V supply. My GSM peripheral using the 3.3V Uart port for a dedicated time (2sec) then turn back to 1.8V level of UART.  Could you offer 3.3V tolerant pin? I am using PA8 to communicate with GSM module. thank you & best regards, feramuz karşil 

Heyho,using L073 at 32MHz, so even I2C transfers "seem" fast, at least in "fast mode plus" at SCL 1 MHz. And I don't want to over-use clock stretching.I'm looking for a way to use I2C slave receive with DMA, but an unknown transfer length.Right now it looks to me as if I could do the following:I2C & DMA prep: all stuff & addresses set, DMA in I2C enabledon I2C ADDR match interrupt:set DMA CNDTR to max buffer lengthenable DMA on I2C STOP match interrupt:disable DMAAny problems with that?Have only 1 device for now...Thanks!

One of my friends noticed, that ST NRND'd not only the STM8, but also the whole STM32L1xx family.However, in contrast to STM8, the 'L1 are under the 10-year commitment program, so they should continue to be available in the next 9 years. JW

Hi,I've have to port an existing huge application from F4 to a H753 board. The F4 has PNOR the H7 dual QSPI flash.One task parses XML configuration data from PNOR flash. A second task stores data e.g. log data in same PNOR.Parsing configuration data use of string functions which require a memory address, while writing to QSPI requires indirect mode. This would require kind of flash memory management, which I guess is bit tricky to handle.I started using indirect mode only and DMA to read chunks of data into memory buffers before parsing it. This works fine. A QSPI read request can suspend an ongoing erase operation, so it is not blocked or delayed. Great.But compared to the PNOR read, the latency when reading data chunks into buffers in indirect mode drops the data processing performance. Therefore I want to check if using memory mapped mode is worth some time spent for investigations.I've read that QSPI read has a prefetch buffer. Is this m

I've built at least a dozen boards using the same communication interface -- a custom debug monitor for communication through stlink -- all on stm32l42x processors. The debug monitor looks roughly like the following code. Although the macros are for ChibiOS, their purpose should be clear.Basically, the host software, after attaching to the debug interface, communicates by passing small commands through DCRDR and getting 32 bit results (which may be memory addresses) in DCRDR.  The DEMCR is used for triggering the monitor interrupt and the MON_REQ bit is used as a semaphore.  This has worked great until now.  I received prototypes of a new design.  Reading/writing of DCRDR works fine, but writes to DEMCR have no effect.  I can debug the code on the board with gdb, and I can write test code that triggers the monitor interface running on the board and even stop in the monitor with a breakpoint, but I don't seem to be able to write a value to

Hello I've been using a STM32L073RZ-Nucleo with a X-NUCLEO-IOD02A1 to test some functions and it works great. But the thing I'm wondering is if its possible to also add X-NUCLEO-PLC01A1 expansion board while using X-NUCLEO-IOD02A1 at the same time.  What steps do i have to take take in software / hardware to make this function? I'm kind of a beginner so if you can just point me in the right direction to where I can find this information it would be very appreciated. Thank you!

Dear all,I have a working camera + video encoder solution running with LCD display disabled.I have one preview thread that displays camera data on the LCD, this thread can be suspended and restarted. While the first run looks fine, the output has a green tint from the second start on:First iteration: Second+ iteration:

Hi, I want to acquire an audio signal from the microphone IMP34DT05 which is connected to the SAI interface of my STM32WB5MM-DK demo board in this way: L/R -> VDD; CLK -> SAI_CK2; DATA -> SAI_D2.The part number I chose is STM32WB5MMGH6TR in STM32CubeIDE. I faced difficulty with SAI interfacing. I tried to enable SAI_CK2 and SAI_D2 and configured SAI A in Pulse Density Modulation (PDM) mode for microphone pairs (1–2), using CK2 as the clock. I also added additional microphone pairs (3–4).I tried different configuration in the SAI_Init() function but in any case it doesn't work. This is the configuration I'm using: hsai_BlockA1.Instance = SAI1_Block_A;hsai_BlockA1.Init.Protocol = SAI_FREE_PROTOCOL;hsai_BlockA1.Init.AudioMode = SAI_MODEMASTER_RX;hsai_BlockA1.Init.DataSize = SAI_DATASIZE_16;hsai_BlockA1.Init.FirstBit = SAI_FIRSTBIT_MSB;hsai_BlockA1.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE;hsai_BlockA1