STM32 MCUs Products

Hi,I am currently developing a small application with a STM32U5 where I write a few bytes into flash using HAL_FLASH_Program(). All seems to work fine. Except I can only read the data back after I do a reset. I suspect that DCACHE is playing a trick on me? But I am not sure how to invalidate the DCache (preferably only for a small section)SCB_InvalidateDCache();Seems to have some problems on the STM32U5? At least, I was unable to include the prober h-file w/o getting tons of errors. What is the new strategy for cache invalidation? Thanks,Juergen 

Good day folks,I have the DCMI camera interface on a STM32N6 streaming to the SDCard, and I am noticing that there are cases that the DCMI reports an Overrun when a SD access occurs at the same time that the Hsync interrupt was meant to occur.Digging into it I believe its due to congestion on the underlying AXI bus, and the IDMA of the SDMMC taking priority over the DCMI DMA. I have set the DCMI and its DMA to the highest possible priority as below. HAL_NVIC_SetPriority(GPDMA1_Channel12_IRQn, 0, 0); HAL_NVIC_EnableIRQ(GPDMA1_Channel12_IRQn); HAL_NVIC_SetPriority(DCMI_PSSI_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DCMI_PSSI_IRQn); HAL_NVIC_SetPriority(SDMMC1_IRQn, 5, 5); HAL_NVIC_EnableIRQ(SDMMC1_IRQn); gpdma_dcmi.Instance = GPDMA1_Channel12; gpdma_dcmi.Init.Request = GPDMA1_REQUEST_DCMI_PSSI; gpdma_dcmi.Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST; gpdma_dcmi.Init.

Hello,In my project, I want to hold boot params in BKPSRAM so "Application project" can also write and read this section easily. If boot is needed, "Application project" will set boot params as required and after that it will use "NVIC_System_Reset".Therefore, I tried to write and read some parameters in this area. I can see the datas is written successfully in "BKPSRAM_BASE_S" section while debugging but when I restart the debug session, BKPSRAM section is all fill with zeros. I know that I am missing something but did not find it. - STM32N655 custom board. #define BKP_SRAM_START_ADDRESS ((uint32_t)BKPSRAM_BASE_S) #define BOOT_PARAMS_PTR ((BootParameters_t*)BKP_SRAM_START_ADDRESS) /* USER CODE BEGIN Init */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_RCC_RAMCFG_CLK_ENABLE(); __HAL_RCC_BKPSRAM_MEM_CLK_ENABLE(); HAL_PWR_EnableBkUpAccess(); HAL_PWREx_EnableBkupRAMRetention(); /*

HI,I am working on a board using STM32H573V and have a working solution with UCPD detecting an inserted memory stick and running the MSC class. In an other part of the software I am using PC9 as an GPIO push-pull, low speed output and as soon as I set it to high, the voltage at PB14 (UCPD CC2) drops from 3.3V to 1.5V and my UCPD handler signals a device attached and turns VBUS on even though nothing is attached. There is no other electrical connection between PC9 and PB14 on the board. I am using a TCPP03-M20 for VBUS switching. The board is acting as VBUS source.

Hello all,I've designed a board around a STM32H743 (LQFP-100) and am running into the following issue.On 2 boards out of 10, the HSE seems not to start properly. The HSE_RDY flag is never set after enabling HSE. I have checked it's not in bypass mode. On the other boards, it works perfectly.The crystal is a ABM3B-8.000MHZ-10-1-U-T and the load caps are 10 pF. We checked possible soldering issues, tested different load cap values just to see, and even replaced the crystal on the failing boards - to no avail.Looking at the OSC_IN/OSC_OUT signals (PH0/PH1) on a scope does not show a significant difference between the working and non-working boards. Maybe just a very slight difference in p-p amplitude.I have looked at the AN2867 app note, and the gain margin seems sufficient according to the formulas given there. I have heard that this crystal may have a bit too high ESR (200 ohm) for the STM32H7 HSE, but again, the gain margin seems alright.

Should each vdd pin of the stm32f407zgt6 read continuity like the blue pill on multimeter, are they internally connected within the chip or separated? Similary for all the vss pins are they also all connected vss inside stm32f407zgt6 Thanks

Hello everyone, I am Li Weiwei (李炜炜) from  a company based in Shenzhen, China, specializing in integrated circuit testing equipment and related R&D. We are currently working on a small-scale R&D / prototyping project that requires the STM32F103TBU6 (VFQFPN36 package) in bare die or wafer form (Known Good Die / KGD preferred), rather than packaged chips. Has anyone here successfully sourced STM32F103 series (or similar STM32F1xx) as bare die / wafer through ST directly, authorized distributors (e.g., Avnet, WT Microelectronics, WPG Holdings, Excelpoint, etc.), or other specialized bare die suppliers? Key details I'm looking for: Is the bare die / wafer option officially available for STM32F103TBU6? (I couldn't find it listed on the ST eStore, public datasheets, or standard channels.) Typical MOQ (minimum order quantity) — e.g., full wafer, partial wafer, or small engineering samples (our target: equivalent to 1–5 wafers o

I tried doing an OBD2 request via Car's OBD2 port.I am able to see the CAN BUS traffic using an oscilloscope , just my request frames are rejected by car. I am using STM32h735G-DK development board to send OBD2 requests. It consists of an inbuilt FDCAN transceiver. Settings are fine (removed termination resistor as car already has two), baudrate is 500kbps  with 87.5% sample point. I am using the following code to send OBD2 request frames:I am able to receive CAN frames and able to log CAN frame frames it is just that frames sent are rejected. What am i doing wrong here?FDCAN Code excerpt: /* ============ 500 kbit/s Bit Timing Derivation ============ * * Step 1: FDCAN Kernel Clock * fCAN = 80 MHz (from Clock Configuration) * * Step 2: Prescaler * Pr

There is something strange happening with STM32N657x0HxQ MCU when HAL tick timer is not using SysTick, but a timer like TIM6, and TIMPRE is changed to 4 or 8 while timer is active. Observed it on DK and custom board.I created isolated test code with CubeMX v6.17.0 for STM32N6570-DK and STM32CubeIDE v2.1.0 to reproduce the issue. IOC file and code in attachment. Test code is in FSBL and it just blinks LED1 with 1 second period. When TIMPRE is 1 or 2, it blinks correctly. To reproduce: Change TIMPRE to 4 or 8 in clock tree and generate + build the code:Power up the board in development mode (BOOT1 = 1). On real application it only happens on cold boot. With this tes

Hello,Document: RM0090 Reference Manual for STM32F405/415, STM32F407/417, STM32F427/437 andSTM32F429/439.https://www.st.com/resource/en/reference_manual/rm0090-stm32f405415-stm32f407417-stm32f427437-and-stm32f429439-advanced-armbased-32bit-mcus-stmicroelectronics.pdfRevision: 21, 07-Jun-2024.Location: Pages 847-862 in Section 27. Also, Figure 241, 242, 243, 244, 245, Table 125.This section, figures and table all contain 17 references to ITEVFEN bit, supposedly from I2_CR2 control register.In reality, there is no such bit in this register, the actual name is ITEVTEN (interrupt event enable), and it is located in I2C_CR2, bit 9.Section 27.6.2 has correct name.stm32f405xx.h file, and others

Hi,I'm working on STM32N6 with CubeMX + X‑CUBE‑AI to deploy a neural network model.The first AI model works fine: no compile errors, runs normally.When I replace the neural network model in CubeMX and regenerate code, I get dozens of compile errors (undefined reference, multiple definition, missing files, etc.).Clean project in IDEDelete build / Objects / Listings foldersReimport the new model in CubeMXRegenerate code completelyI have tried:But the issue still exists. It seems old AI files are not cleaned properly when changing models.Has anyone faced similar issues on STM32N6 when switching AI models with CubeMX + X‑CUBE‑AI?How did you solve this? Thanks for help.

Hi everyone,I am currently looking into the STM32F303CCT6 and I'm a bit confused by the ADC specifications. ST's website mentions it can achieve up to 18 MSPS in interleaved mode. However, looking through the Datasheet and the Reference Manual (RM0316), I don't see a clear way to hit 18 MSPS at 12-bit resolution.I realize the hardware interleaved mode is only dual (e.g., ADC1/2 and ADC3/4). Since the documentation mentions dual mode can reach up to 9 MSPS at 12-bit, and there is no nati

Hello,I am trying to use the I3C interface between STM32H523 and DDR5 SPD. I have found a question would like to be answered: Is there any way to send the broadcase address (7'h7E) with SCL signal configured in I2C timing characteristics?According to MIPI I3C Basic specification v1.1.1, page 366, Table 86 I3C Open Drain Timing Parameters, note 9,The Controller uses this timing to send the first Broadcast Address after Bus initialization, in order to disable the I2C Spike Filter for applicable I3C Target Devices (see Section 5.1.2.2.2) (At least 200ns)

I'm reading RM0492 Rev 3 about I2C's controller transmitter. The original words on the page of 1185 areWhen RELOAD = 0 and the number of data bytes defined in NBYTES[7:0] is transferred: • In automatic end mode (AUTOEND = 1), a STOP condition is automatically sent. • In software end mode (AUTOEND = 0), the TC flag is set and the SCL line is stretched low, to perform software actions: – A RESTART condition can be requested by setting the START bit of the I2C_CR2 register with the proper target address configuration and the number of bytes to transfer. Setting the START bit clears the TC flag and sends the START condition on the bus. – A STOP condition can be requested by setting the STOP bit of the I2C_CR2 register. This clears the TC flag and sends a STOP condition on the bus. When a NACK is received, the TXIS flag is not set and a STOP condition is automatically sent. The NACKF flag of the I

Hi , I have developed a testcase where STM32H503 i3c is in target mode, requesting for controller role request that is going to controller (checked interrupt - Secondary Controller received Controller Role Request ) . After controller is sending GETACCCR command to target but in target side I3C_EVR.CCRUPDF bit is not set. Can you please guide me how to check CRR request. 

This is looking for more info from this original post * https://community.st.com/t5/stm32-mcus-embedded-software/i-am-using-usb-pd-system-with-stm32g071rb76-processor-there-are/m-p/219760#M53483     With a stm32 chip with only one CC line could i connect both of the CC lines together. This is a DFP I don't need VCON support If i were to do this could i still figure out what the orientation is?  

Hi, I’m trying to configure the FDCAN peripheral on a NUCLEO-STM32H72ZG board, but even though it works perfectly in loopback mode, it doesn’t work when I switch to normal mode. Even in external loopback, when I check with the oscilloscope I don’t see any activity on the TX pin (no signal transitions). The same issue occurs on this board also with GPIOs. I tried the same setup on a NUCLEO-STM32F303RE board (using CAN instead of FDCAN), and everything works perfectly there.      

Dear all,I'm implementing Over-the-air firmware updates for a board using the STM32N657 MCU.In the Appli, I download the new firmware binary over Wifi and store it to RAM at a fixed location in AXISRAM5 and 6. In order to flash the new binary to the OctoSPI Flash I prepend a "magic" header to the new firmware binary (still in RAM) and then restart the MCU using `HAL_NVIC_SystemReset`. Then, after this reset the FSBL checks the fixed location in RAM for the "magic" header. If present, it should flash the OctoSPI Flash with the new firmware binary using the ExtMem Manager (I cannot just flash directly from Appli because I use XIP and hence the Appli is running from OctoSPI in memory-mapped mode, preventing writes). I've done similar things with other MCUs and it worked perfectly fine.However, it looks like on the STM32N6, the contents of AXISRAM5 and 6 are not preserved across software resets. At least, checking the "magic" header in FSBL always produces randomly

Heyho,I recently found that I'm not using ITCM RAM at all, then started to put heap and stack there.No problems so far.Then I copied some functions there, and all went well - until I found some strange behaviour:1..4 SAI RX DMA transfers running, circular modewhen all these transfers are complete for each SAI, a function is called to copy the complete DMA buffer from internal AXI SRAM into the big buffer in HyperRAMalso in this function a packet counter (a global u32 in DTCM) is incremented oncebut when this function is in ITCM, this packet counter increments for each SAI active, but there are no extra packets Further info:- instruction cache: in use- data cache: not used Is there any guideline what to put in ITCM, what are the limits, etcpp. ?

hello, where can i download win11 STM virtual com port?  i install both VCP_V1.5.0_Setup_w7_x64_64bits and W8_x86_32bit all not working ! i din seeSTM Virtual Com port at device manager! only STM STLink visual com port appear ... 

Hello,in our design with STM32H753ZIT6 I've adjusted the C0G load capacitors on the LSE 32.768 kHz crystal so that the real-time clock is now very accurate (less than 1 second error in 24 hours). I've always performed the calibration in VBAT mode at a voltage between 2.3 and 3.2 V.However, now I've noticed that in normal VDD mode with active controller, the real-time clock is running significantly too slow, with an error of 90 seconds in 24 hours. I've ruled out the VBAT supply voltage as the cause. Any ideas what could be causing this large error in normal VDD mode?Thank you!

Hello i use STM32G070CBT6 with PD0 and others pins.PD0 as input pin with no internal pull-up/down with extrenal 10k pullup gives only 0.7V, when i set the pin to output and set state to high there is 3.3V.Where is the problem? 

Dear ST Community,I am currently migrating my Firmware from STM32H723VG to STM32H563VI. I have problem with Internal Temp Sensor. Based on Reference Manual on both MCU reading temperature is the same, but it doesn't work as it should.When on STM32H7 I got about 750 (24 degree Celsius) on reading ADC from TEMP Sens, on STM32H5 I have around 100.I tried both with and without cache (ICache and DCache), with Bare Metal and Zephyr RTOS code. In every configuration it is not working. I tried also on different MCUs, so it shouldn't be part itself.It worked with Nucleo H563ZI, but doesn't with H563VI.What else can I do?

Hello,I want to change for boot to use XSPI1 interface, but I am not sure about OTP bits, there in description some bits is not very clear, what OTP bits to set to switch if it's possible ?Additionally if I will use SD card for boot I can set OTP11 value to 0x00000020 (bit5 = 1 = sdcard), write FW to sd and use sd for boot source ?Thanks.

Say I am operating as master with CPOL=1.  Because the NSS pin seems to lag the enable bit (SPE) slightly, my logic analyzer always barfs on the first SPI packet because the clock is in the wrong state.So, I set the GPIO to have a pullup on the clock in CubeMX and the problem goes away - as soon as the init functions run, the clock goes high and stays that way until the first SPI transmit.  Also, the clock stays high after the end of the transfer if the SPI is disabled in the callback function.My only concern is for power consumption: It is obvious that the pullup gets applied when the SPI is disabled but I don't know is if the pullup applied all the time even when the alternate mode of the GPIO is set, i.e. is the pullup still applied at the pin when the SPI is enabled?  Do clock pulses during an SPI transaction work against the pullup?