STM32 MCUs Products

I'm working on a design with an STM32L072CZT6TR, where I want to calibrate my main timebase. That main timebase is TIM6, which counts 16,000. The HSE is 16MHz, so there's an interrupt evey 1ms. Calibration is done by counting the number of HSE cycles between two consecutive PPS pulses from a GPS receiver. The PPS triggers an EXTI interrupt, which starts TIM21 and TIM22 at 0 on the first pulse, and reads the timer values on the second.TIM21 is set to count 16,000 pulses and TIM22 is slaved to TIM21. This way, I can conveniently determine whether the HSE is slow (TIM22 == 999) or fast (TIM22 == 1000), and calculate a correction based on TIM21.This logic is copied straight from an older design with an STM8, where it works like a charm. However, the cascading does not work. No matter what, TIM22 is always 0 on the second PPS. I have used CubeMX to set the timers up, and, going over the code with

Hello,I’ve recently started using ST products and the IDE with CubeMX, which is why I’m asking for your help. I’ve just begun developing a communication system using a Nucleo H743ZI2; my goal is to set up a UART and a CAN bus.The UART is done; I used DMA access to optimize it. However, when I try to enable the CAN bus in Cube MX, I run into a problem with the clock configuration related to the bus.When I use the “Resolve Clock Issues” function, I get the error: “Cannot find a solution for some constraints.” Does anyone have any ideas to help me solve this problem? Thank you in advance, and have a great day,

For STM32H7, if the FMC data lines and SDRAM data lines are cross-connected (not D0 to D0), and address lines are also cross-connected (not A0 to A0), can SDRAM work properly? My PCB is about to be manufactured, but due to the hardware engineer’s design, the SDRAM data lines and the MCU’s FMC data lines, as well as the SDRAM address lines and the MCU’s FMC address lines, are not connected one-to-one according to the CubeMX standard. Instead, the order has been shuffled. The actual wiring relationships are as follows: Data line connections: MCU FMC_D0 is connected to SDRAM_D13MCU FMC_D1 is connected to SDRAM_D14MCU FMC_D13 is connected to SDRAM_D1MCU FMC_D14 is connected to SDRAM_D0MCU FMC_D4 is connected to SDRAM_D7MCU FMC_D5 is connected to SDRAM_D6MCU FMC_D6 is connected to SDRAM_D5MCU FMC_D7 is connected to SDRAM_D4Address line connections: MCU FMC_A0 is connected to SDRAM_A2MCU FMC_A1 is connected

According to the PD 3.1 requirements (also PD 3.0), I need to connect UCPD1_CC1 and UCPD1_CC2 to USB-C CC1 and CC2 to communicate and request the desired voltage. But STM32G0B1KBU6  has only UCPD1_CC1 available. Is there any way to connect STM32G0B1KBU6  to USB-C to comply PD 3.1 requirements?

Hello,the SPI does work with NSSP(Negative Slave Select Pulse-Mode), but it does not work if I disable NSSP. As someone pointed out the SPI NSS(P) may only work if the Pulldown of that pin is enabled, but I’m not 100% sure on that one, but it seems to wirk for NSSP-En that way. For NSSP-Disabled I could not get the SPI-Controller to control the NSS(CS).I observed two issues:1) On Reset the NSS(CS) is low and will stay low until the first SPI Transaction. I tried to set it via HAL_GPIO_WritePin( … , GPIO_PIN_SET); but that has no effect, maybe because the Pin is controlles by the SPI-HW.2) Is the serious issue is, if I disable the NSSP, the CS does not work at all.How can I make the Hardware NSS work with NSSP disabled?Thanks a lot, Best Regards, SeppelP.S.This is the Setup and Waverforms for the NSSP-Disabled, I have a 2s delay on startup, which you can see on the sc

Hi,is there any HW guidelines to configure a USB OTG port with STM32H563VIT6 with VBUS detection?

Hello.I recently experienced an unusual MCU Problem and need to analyze it. Please help me. The FW program download to the MCU is successful, but it does not operate after a reset. I performed a short circuit test after disconnecting the power(Battery)but even when measuring VCC-GND and GND-VCC at the power supply, a resistance value of approximately 500 ohms is detected. When I disconnect only the MCU from the PCB and re-measure, the 500 ohm value disappears from the PCBbut this value persists when measuring directly from the MCU pins. Can I conclude that the MCU is dead due to a power supply failure?And in what cases does this problem occur?

New question split from this post.One additinal request: When checking if bootloader pin configuration has an impact on the real application it would be helpful to know the default level for output pins, likedoes the UART_TX pin drive active high or low?does the boot loader drive the SPI MISO output pin HI, LO or Z?is the CAN_TX pin drven HI or LOW?Thank you!

Hi,When reviewing the descrption of MCU pins used by the integrated system bootloader, I came across several documentation bugs in the latest AN2606 (rev70). Inparticular, Table 164 lists:USART1_TX pin - PA9 pin: USART1 in transmission mode. Used in input no pull mode: Input mode for an output pin? Same issue with USART2 and USART3.SPI1_MOSI pin - PA7 pin: slave data input line, used in push-pull, pulldown mode: Input pin does not have push-pull mode.SPI1_NSS pin - PA4 pin: slave chip select pin used in push-pull, pulldown mode: NSS ist used as an input, so it does not have push-pull mode.Same issues with SPI2 descrpition.The same problems are in Table 166. I have not checked the tables for the other CPUs, but I suggest a review of the document might reveal more issues.RegardsNorbert Unterberg   

I'd like to use a general purpose timer to continuously trigger a rtc timestamp (using H533)Is it possible ?How to map TRGO signal to Timestamp trigger ?(No HAL please, LL or direct register setup).Thanks in advance.

im having trouble displaying my own bitmap what converter should i use to convert a bmp file to array to work with this function 

Hi, EveryoneI am trying to setup STM32H7R7Z8 XSPI2 in Quad mode for APS6404L-3SQR QSPI PSRAM.The original code is generated from MX v6.116.1 and developed with IDE v2.0.0.HW info:The PSRAM is connected to XSPI2 with NCS, CLK, IO0~3. There is no DQS pin (PSRAM does not support it).The XSPI2 is setup in 133MHz frequency PSRAM supported.APS6404L-3SQR: 133MHz for 32 Bytes Wrapped Burst, 64Mb, 8M x 8bits, pagesize 1024 bytes,SW configuration:/* XSPI2 parameter configuration */ hxspi2.Instance = XSPI2; hxspi2.Init.FifoThresholdByte = 4; hxspi2.Init.MemoryMode = HAL_XSPI_SINGLE_MEM; hxspi2.Init.MemoryType = HAL_XSPI_MEMTYPE_APMEM_16BITS; hxspi2.Init.MemorySize = HAL_XSPI_SIZE_64MB; hxspi2.Init.ChipSelectHighTimeCycle = 2; hxspi2.Init.FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE; hxspi2.Init.ClockMode = HAL_XSPI_CLOCK_MODE_0; hxspi2.I

HI ALL.I am using MB1549C board with NUCLEO-U5A5ZJ-Q cpu.SD card is connected to SDMMC1 pins 4bit mode.HAL code is generated with CUBE MX.During SD card initialization CMD8 command is sent.I see that after it sent some flags are set which relates to DPSM.But CMD8 does not require data transfer on D0 pin.So DPSM must not be enabled. But I see these flags in STAR register.BUSYD0,DPSMACT,DTIMEOUT.Response is received correctly but why DPSM is enabled and of course timeout error occur becausethere is no and should not be data on D0?Thanks

Hi I am trying to set up hardware SPI using the following. My software SPI works fine, but the hardware SPI doesn't even have a clock signal.   /** ****************************************************************************** * @file : main.c * @brief : P7-SPI2: Two bursts, same 6 bytes. Burst1: SW SPI (PE2/PE6). * Burst2: Hardware SPI1 (PA5/PA7). Probe D0=PE2, D1=PE6, D2=PA5, D3=PA7. * HW SPI1: kernel clock per_ck, GPIO before SPI, CSTART errata workaround. ****************************************************************************** */ #include <stdint.h> #define RCC_AHB4ENR (*(volatile uint32_t *)0x580244E0u) #define RCC_APB2ENR (*(volatile uint32_t *)0x580244F0u) #define RCC_D2CCIP1R (*(volatile uint32_t *)0x58024450u) #define GPIOA_MODER (*(volatile uint32_t *)0x58020000u) #define GPIOA_AFRL (*(volatile uint32_t *)0x58020020u) #define GPIOA_ODR (*(volatile uint32_t *)0x58020014u

Hi, I have a custom STM32N6 board where the BOOT0 and BOOT1 pins are tied directly to ground under the BGA with no test points or jumpers. Is there anyway to connect a debugger in this scenario or is my board bricked? Below is what I get when attempting to connect via an ST-Link V3: >STM32_Programmer_CLI.exe -c port=SWD mode=UR -rst ------------------------------------------------------------------- STM32CubeProgrammer v2.21.0 ------------------------------------------------------------------- ST-LINK SN : 003700163431511731343632 ST-LINK FW : V3J17M10 Board : STLINK-V3MINIE Voltage : 3.26V SWD freq : 8000 KHz Connect mode: Under Reset Reset mode : Hardware reset Device ID : 0x486 Revision ID : Rev Z Device name : STM32N6xx Device type : MCU Device CPU : Cortex-M55 BL Version : -- MCU Reset Error: Unable to run MCU! Error: Error code: 32 And this is what I get from the STM32CubeProgrammer GUI:

Hi everyone,I tried to manage the USAR LIN break detection interrupt using only HAL driver functions but I did not find a way to do that. I had to modify the file stm32f0xx_hal_uasrt.c adding some code to manage the LIN break interrupt.Is there a way to detect the LIN break in my application without modifying the driver code?This is the code I added to the aforementioned HAL driver file:// At the beginning of the file, where other prototypes are placed   #if defined (USART_CR2_LINEN) extern void HAL_UART_LINBreakCallback(UART_HandleTypeDef *); #endif   //...   // Inside function HAL_UART_IRQHandler   #if defined (USART_CR2_LINEN) /* UART LIN break has been detected ----------------------------------------*/ if(isrflags & USART_ISR_LBDF) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_LBDF); /* Call the callback function to signal LIN break detection */ HAL_UART_LINBreakCallback(huart); } #endif /* USA

Hi, I want to go to sleep/stop mode with STM32 and wake on interrupt. After last interrupt it should wait for 10sec and go back to sleep. But I see an edge case where interrupt could occur just before going to sleep/stop mode.How do I handle interrupt just before going to sleep/stop mode (cancel sleep/stop mode)?Basically force WAKE from sleep/stop mode even if STM32 is not yet in sleep/stop mode?  #define STAY_WAKE_FOR_TICK 10000 static volatile uint32_t GoToSleepAfterTick; void main(void) { //... while (1) { HAL_SuspendTick(); HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI); HAL_ResumeTick(); while (HAL_GetTick() < GoToSleepAfterTick) { //... } // interupt could occure here??? } } void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { if (GPIO_Pin == CALL_Pin) { GoToSleepAfterTick = HAL_GetTick() + STAY_WAKE_FOR_TICK; } }  

 I need support to get IAP over SPI.I've esp connected to my stm32u5 over SPI. Stm is slave and ESP is master. For stm I've created project using stmcube by entering MCU part number.Now here my question is1. Do I need to develop bootloader code to achieve this.2. How do I customise bootloader code.3. STM boot pin is connected to ESP. do I need to control this?4. Hwi do I adjust my memory or linker file

Hi,I have this question because the reference manual states:“When flash high-cycle data area on Bank1 is enabled, the code memory map is not continuous from Bank1 to Bank2 on 2M- and 512K-byte devices.”So, does this mean that enabling high-cycle data sectors as EDATA on a 1MB device does not affect the code memory space, while on 2MB and 512KB devices, some sectors are reassigned for EDATA usage? If that’s the case, it seems like the 1MB device effectively has an extra 96KB of high-cycle data memory.Snaku

We had:An STM32H7Sx with an external flash on one XSPI port, and an external RAM on the other;Both external devices memory mapped;The core clock running at 380 MHz.XPI1 mapped to port 2, and vice versa.XSPI clock running at 200 MHz.Using our adapted version of ST's secure bootloader, we erased sectors of the external flash, but found that this consistently caused corruption in the external RAM, and it also looked like the erases weren't fully successful either.The driver code which carried out the erases removed the flash from the memory map before each operation, and added it back afterwards.We found that to avoid the RAM corruption, it was necessary to also remove the RAM from the memory map before the flash erase operation, and add it back afterwards.We had assumed that the two buses were independent (despite meeting in the XSPIM), so this result was unexpected; and it's still not clear to us w

Hello,I am currently preparing the documentation package for CE certification of a device that uses the STM32G071RB microcontroller.Could you please clarify whether there is any official CE compliance documentation available for this MCU (or for the STM32G0 series), such as:CE declaration or compliance statementRoHS / REACH declarationenvironmental or material compliance documentationany other certificates typically provided for regulatory documentationIf a direct CE certificate is not applicable to the microcontroller itself, could you please advise which official documents from ST are recommended to include in the technical file for CE marking of the final product?A link to the relevant documents or the ST compliance page would also be greatly appreciated.Thank you in advance for your help.Best regard

I see in STM32CubeMX that a STM32G411 exists but it has the status "restricted". I'm curious why this type is not widely available. I'm currently using the STM32G431 in an application, mainly because of its raw clock speed of 170MHz. I don't actually need its analog functions but the flash size might become too tight. In that case, my only option would be to switch to the G491, which is more expensive and contains even more unneeded peripherals... So... why is the G411 not available to the public?

Hi Team,I'm recently using the STM32U5G9ZJT6Q part in one of my design. I couldn't find the package mechanical information in Datasheet. For now, I'm using the LQFP-144 form the STM32H573ZIT3Q part number. Will it be okay? Can you please help to verify it? Attaching the below Screenshots,Screenshot from the STM32U5 Datasheet. Not having the LQFP-144 details.Screenshot from the STM32H5 Datasheet. Having the LQFP-144 details

I am working with the STM32U083RCT6 and I need clarification regarding the exact physical memory addresses of the option bytes.In the reference manual, I can see that the option bytes are located in the system memory area:0x1FFF7000 – 0x1FFF7FFFHowever, the manual only describes the FLASH option registers (OPTR, PCROP1SR, PCROP1ER, WRP1AR, WRP1BR) with register offsets from the FLASH peripheral base address. It does not clearly mention the exact non-volatile storage addresses inside system memory. I would like to confirm:1.What is the officially documented physical start address of the option byte storage in system memory for STM32U083?2. Is 0x1FFF7800 the confirmed start address of OPTR in non-volatile memory?3. If this information is not in the reference manual, in which official document can I find the exact byte-level

Hi, I'm using STM32H745ZI implemented ethernet with Lwip it's working fine STM32CubeIDE(ver-1.90.0) but not in IAR(ver-9.30.1) like any changes that I need to do in .icf  file of IAR because it's working fine Cube IDE