STM32 MCUs Products

Hello, ST expert For GPIO structure, what are the differences between FT and TT mode? Are there any differences for the ESD diode and the other diode in these two modes?     BR Yang  

Hi All,I've just been watching an ST tutorial video on how to implement  bare-metal Device CDC USB  on an STM32U3.During the video, the lecturer says that the code is available within the workshop download. No link is provided to the workshop code....Does anyone know where I can find it? This is the video in question : https://youtu.be/m8ph9JIY5QE?list=PLTJzs51NlEIAHFfePhKJPsnWvT5XidJuU&t=1164Any help would be appreciated.CheersMichael 

Hi All,    I want to do something very basic, but somehow cannot manage to do it. What happens if you have a PWM signal on an IO Pin, generated by a timer, and you disable the timer?  What happens to the physical IO Pin ? Is it stuck at the state where it was when you disabled it ?, Does it go Low ? Or High. The Idle state of the Timer is Low, and the On state High.    Thanks,  DJ 

Hello ST Community team,I would like to report a possible inconsistency in the STM32 MCU Portfolio Selector regarding Ethernet filtering for the STM32C5 series.While selecting MCUs using the Portfolio Selector, I filtered devices through:- EthernetThe reference STM32C593CET6 appears as supporting Ethernet functionality. However, according to DS15136 (Table 1), this specific MCU does not include the Ethernet peripheral.This may create confusion for developers, especially since the STM32C5 family is still relatively new and many users rely on the Portfolio Selector during early device selection.Could you please review and correct this behavior.Ps: more details available on this post. Best Regards.II

Hello everyone,I have encountered a strange issue with my UART transmission function on an STM32 microcontroller operating in Half-Duplex Open-Drain mode.Currently, the function works perfectly fine without checking the TC flag. However, when I add a check to wait for the transmission completion at the end of the function, my logic analyzer shows completely garbled bytes (corrupted data).Here is the code that works perfectly (without the TC check):void send_array(uint8_t *arr, uint8_t size) { /* Receiver disable */ USART3->CR1 &= ~(CR1_RE); for (int i = 0; i < size; i++) { /* Wait until Transmit data register is empty */ while(!(USART3->SR & SR_TXE)){} /* Send byte */ USART3->DR = arr[i]; } /* Receiver enable */ USART3->CR1 |= CR1_RE; }And here is the modification that breaks the transmission and leads to garbled bytes on the a

Hi,I am using the STM32F407VET6 chip to simulate the SENT protocol. I have encountered some issues and would appreciate it if professionals in the forum could provide some answers.1.Since the SENT protocol signal needs to change the output waveform based on the transmitted data, I attempted to use the TIM BURST feature of the chip to simulate the SENT signal. I am configuring it using STM32CubeMX software. Below are the relevant configurations: 

我正在写BootLoader的程序，我想要实现IAP，我目前编译后生成的.bin文件大小为18kb（之后代码多了还会再增加），但是我APPUP区空间为248KB，我的配置为： Translation (by google translator): "I'm writing a BootLoader program and I want to implement In-App Access (IAP). The .bin file I'm currently compiling is 18kb in size (and will increase as the code grows), but my app upload space is 248KB. My configuration is..." 我想要实现生成的.bin文件为248kb，不够的地方自动填充，我的生成.bin的指令如下 "I want to generate a .bin file that is 248kb in size, with automatic padding if necessary. My command to generate the .bin file is as follows:"

The AN3156 explains on page 18 the Read Unprotect Command:This command is selected when wValue = 0 and the first byte of the buffer sent by the host is 0x92. The buffer length is only one (the command) byte.The host sends a DFU_DNLOAD request with the above parameters to remove the read protection of the internal flash memory.   It is very useful that you implemented a command to remove the read protection.But this is useless if there is also a write protection active.The user has no way to remove a write protection over the DFU protocol.Why does this command not remove both: The read protection AND the write protection at the same time?Why does STM implement nothing that allows to remove a write protection ?

The STM32G0B1 has a very ugly bug in the bootloader.When I have a write protection on a flash memory area:WRP1A_STRT = 0x0 --> 0x08000000WRP1A_END = 0x1 --> 0x08000800 and then I upload a new firmware to this area the firmware will not be written, because this area is write protected.This is correct.But it is a horrible bug that I send a USB control request withRequest.Function=URB_FUNCTION_CLASS_INTERFACE;Request.Direction=VENDOR_DIRECTION_IN;Request.Request=DFU_GETSTATUS;Request.Value=0;Request.Index=0;Request.Length=6;Result = STDevice_ControlPipeRequest(hDevice, &Request, (BYTE*)pkDfuStatus);and the buggy bootloader returns STATUS_OK (value 0) instead of STATUS_ErrorWRITE (value 3) The user thinks that the firmware was uploaded correctly but the processor is dead because the flash memory is corrupt.  

Hello everyoneI'm new here, but i have worked on a flight controller unit FCU with those:FMU Processor: STM32H753IO Processor: STM32F103This FCU then connected to a Raspberry Pi4, auxiliary, where  run his drone python software, using MAVlink approach for telemetry data and CAN communication and parameters setup;Right nowWe have a (good) software ready, with some wizard working wellBUTwe have an issue with CAN-motors and our STM chips...Is it possibile that those H753 is NOT able to read a CAN motor ,brand new, out of fabric?or betterIs the chip (H753) ABLE to write a NODE ID on a CAN motor, wich is ut of fabric (nodeID=1) to an actual working NODE ID(10,11,12 etc..)?We had this issue....based on your knowledge..The correct way is to use a CAN-USB to "wake up"

Hello, ST experts It is found that USB_D+&USB_D- pins(PA12&PA11) of STM32U595 in our own design are very sensitive to ESD strike. When USBPHY power is not on as reference manual said, I think it is only 3.3V tolerant in this case, but not 5V tolerant, am I right?And in 3.3V tolerant case, what ESD protection way should do? e.g. USBLC6 can be effective? Best RegardsYang

Hello, I have recently received a shipment of STM32F446RCT6 microcontrollers and I need verification of the ST label for quality assurance and production clearance. Could you please assist in confirming if the attached label and packaging details conform to official STMicroelectronics standards? [Photo removed to prevent bulk ID abuse]

Hi Team,I am working on board design using STM32H745 (LQFP176 package), and I would like to confirm the correct external memory selection for my smart kitchen application.Application details:- MCU: STM32H745 (dual core)- Package: LQFP176- USB OTG FS used as HOST to interface a USB camera- Camera usage: Snapshot (JPEG only, no continuous video streaming)- Current: 2MP- Future plan: up to 5MP snapshot- Additional peripherals:- I2S (audio codec interface)- 4× I2C buses- UART / RS485- 2× SPI For external memory, can I use QSPI PSRAM (APS6404L 8MB), or should I use SDRAM via FMC? Please advise which memory type is recommended.  Any guidance or recommended reference designs would be helpful. ThanksSathiya 

Hi everyone,I have successfully implemented a USB VCP device on STM32G0C1 microcontroller, and it communicates perfectly with my PC.To meet current product trends, I am migrating the connector to USB Type-C (schematic attached). I am keeping it as a USB 2.0 interface. For reference, here is my current pin configuration based on the schematic:GND (Pins 1 & 12): Grounded.VBUS (Pins 2 & 11): Left floating (my device is self-powered and does not require host power).CC1 / CC2 (Pins 3 & 9): Each independently pulled down to GND via a 5.1kΩ resistor.During testing, I encountered the following issue:Using a Type-A to Type-C cable: The PC successfully recognizes the device and it works perfectly.Using a Type-C to Type-C cable: The PC fails to recognize the device at all.

In AN2606 Rev. 70, Chap 90 Device-dependent bootloader parameters table 226 the RAM area accessible from the bootloader seem inconsistant: - C031xx has a negative RAM range, excluding RAM at bottom and top of full RAM range as accessible from the bootloader- C01xx RAM range declares all RAM as accessible - C031xx excludes RAM at bottom and top of available RAM Please confirm these values. Thanks!

Hello,   In the reference manual rm0481 (stm32h562) in chapters 7.11.38 and 7.11.51 it is stated that EDATAx_STRT Bits do not have any hardware effect. Can I assume that the corresponding bits in FLASH_EDATAxR_CUR are set from option bits only? In that case what is purpose of these bits in FLASH_EDATAxR_PRG? Are rhey also set from option bytes? What about the EDATAx_EN bit in FLASH_EDATAxR_PRG? Here the documentation is NOT stating that there is NO hardware effect. Is this correct? If yes, where does the actual setting of EDATAx_EN in FLASH_EDATAxR_CUR come from? By the way in Table 51 there is an DATA_EN1 bit in FLASH_EDATA2R option bytes. May I assume that this is a documentation error and it should in fact be DATA_EN2   Thank you  

Hi ST Community, I am working on STM32H563 with external SDRAM connected through FMC. I am trying to use: heap in SDRAM global variables in SDRAM execution/data access from SDRAM DCACHE enabled Current SDRAM mapping: 0xC0000000 I noticed that in STM32F7/H7 examples there is support for: HAL_REMAPMEMORY_FMC_SDRAM() which remaps FMC SDRAM memory regions internally. I found this in STM32F7 HAL: __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() But on STM32H563 I cannot find any equivalent remap mechanism or SYSCFG macro. My questions are: Is there any equivalent SDRAM remap functionality available on STM32H563 / STM32H5? Is SDRAM fixed permanently at 0xC0000000 on STM32H5 architecture? Does STM32H5 treat SDRAM at 0xC0000000 differently regarding: DCACHE burst accesses MPU memory attributes

C5  implements a way to de-activate selected boot devices. This will allow to use the system bootloader on custom board were some activity on pins used by the bootloader but not used for the bootloader would inhibit use of the bootloader. This feature has been requested before and is very welcome. However neither in RM0522 nor in AN2606 I find the explanation for the fifferent bits. Did I miss something?

Dear Team,           Currently we are seeing part below in stock, Can we know if the parts were also assembled in China. Can you please check and confirm on the same. We are planning to procure 250# for production purpose.  MPN: STM32H533CET6 (or) STM32H533CET7Source: STMicroelectronics 

Dear Team,       We are currently using STM32H523CET6 in our designs. Can you please let us know if there any one is to one non- chinese alternative for the same. Please provide your support on this by treating this as critical, because we are holding our production.NOTE:Country of Origin/ Country of assembly/ Country of Manufacturing is NOT CHINA.  

 Hi everyone,I am working on an STM32H523 MCU and I have recently observed some strange behavior regarding the PB14 and PC9 pins. I have the following setup:PB14 is configured as input (I use this for the TIM2_CH2 alternate function, but this does not affect the issue) and is externally pulled up using a 10kOhm resistor.The PC9 pin is configured as output.When the PC9 pin is unset, the PB14 is 3.3V, as expected. But when setting the PC9 pin, the voltage on PB14 drops to only 1.13V.  These pins are otherwise not connected, so 2 seemingly unrelated pins seem to have some dependency within the stm32h523 chip.  Another test was performed by configuring PB14 as output (without pullup). Now, when PC9 is unset and PB14 is set, the voltage on PB14 is 3.30V. When setting PC9, the PB14 voltage drops to 3.26V, which seems related... To make sure it is not caused by our own har

I have a custom STM32H755IIK6 board where ADC1 and ADC2 are used as an I/Q receiver. The ADCs are configured in dual regular simultaneous direct mode, 12-bit, at 1.92 MSPS per channel.The board also includes a LAN8742A Ethernet PHY. The 50 MHz RMII reference clock trace is routed close to the ADC pins (ETH_REF_CLK on P2, ADC inputs on P3 and R3).Both STM32H755 and LAN8742A use separate 25 MHz crystals.ADC clock configuration:PLL2P = 30.719995 MHzDIVM2 = /5DIVN2 = x153DIVP2 = /25FRACN2 = 4915I observe a periodic spur pattern with peaks at:93.75 kHz280.31 kHz466.88 kHz653.44 kHz840.00 kHz 

Hi, I am using STM32G491 with 2 FDCAN channels. FDCAN1 is working normally for sending and receiving data. FDCAN2 is sending out data normally, but it can't receive any data, not able to generate any receiving interrupts. Here is the initialization code. Can anyone have any ideas what could be the issue? Thanks.  void MX_FDCAN2_Classic_Init(void) { FDCAN_FilterTypeDef sFilterConfig; __HAL_RCC_FDCAN_CLK_ENABLE(); hfdcan2.Instance = FDCAN2; hfdcan2.Init.ClockDivider = FDCAN_CLOCK_DIV1; hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC; hfdcan2.Init.Mode = FDCAN_MODE_NORMAL; hfdcan2.Init.AutoRetransmission = DISABLE; hfdcan2.Init.TransmitPause = DISABLE; hfdcan2.Init.ProtocolException = DISABLE; //CAN 500kbps hfdcan2.Init.NominalPrescaler = 16; hfdcan2.Init.NominalSyncJumpWidth = 1; hfdcan2.Init.NominalTimeSeg1 = 2; hfdcan2.Init.NominalTimeSeg2 = 2; hfdcan2.Init.DataPrescaler = 1; hfdcan2.Init.

Hello, we are seeing a weird symptom in our application in which all LTDC registers are reading back the same seemingly random number.  This is during a debugging session via system viewer (we are using Keil 5.40 and compiler 5), OR when reading and printing out values to serial at runtime.  The LTDC seems to be operating properly (mostly, working through various issues but it's displaying graphics at least.  I'm stumped, and so are the AIs I use.  Any ideas as to why this might be? 

Is there a STM32N6 throughput test on the USB 2-480Mb happened.   I'm just curious because i'm getting a throughput on my design of *  97 Mb    Just wondering what is a idealistic throughput to see if i need to edit something on my end or this is a expected throughput to get.