STM32 MCUs Products

The Reference Manual (RM0454) of the STM32G0B0 points to an old 2020 revision while on the website it shows 2025.I believe this is a mistake since there should be a newer revision of this RM with the fixed Flash section (STM32G0B0CE) unless ST only fixed the RM of the STM32G0B1.

Here comes another query about the status of a HUB device for the USB Host library. I have been working with the driver from herehttps://github.com/moribr/STM32F4HUB/blob/master/Project/Middlewares/ST/STM32_USB_Host_Library/Class/HUB/usbh_hub.cand have the HUB functional but cannot seem to get the MSC initialized and working. Why does STM not support a hub in their HOST Library? There certainly have been enough inquiries.

Hello. I have a custom board with original f103c8t6 (sampled from eStore). PWM for pin PB4 is not functional, but bit banging with gpio write works. If tim3 respective channel is configured as pwm output, the output is stuck at VCC.  I configured the board correctly in CubeMX, as every other pin works correctly (including pin PB5, same timer, different channel) and double checked it again and again. Unfortunately I can't attach a project that reproduces the bug at the moment as I moved forward by changing the operating mode of the board (it commands a MC33926PNB H bridge and instead of having the H bridges enabled and sending PWM over IN1 and IN2, i set them as high or low depending on the direction and pwm the enable input, which functions well), but in a few days I can reproduce it. I am curios about what can cause the strange behaviour. It's not a conflict between JTAG reset as I have SWD enabled and even disabled it for a test which led to t

Hello everyone, I am quite new to this and I am using the STM32G474RET6 with BOR level 4. I changed the BOR level to level 0 and the board did not work properly. After changing it back to level 4, everything worked fine again. Is there any relationship between CPU speed (it is 168Mhz in our case) and BOR level?  We are not sure how to properly select the BOR level.    Thank you.

Our product is battery powered and uses an STM32L072CZT6.I did not write any of the power management code and I am not sure exactly what modes are used.When cold started and left to go into power saving mode, the current drawn by the entire product averages 82uA.However, after changing BOOT0, resetting, flashing the app using STM32CubeProgrammer, changing BOOT0 back, resetting again and letting the unit run until power-saving mode engages it then has an average current draw of 200uA, a 150% increase. I also discovered that re-flashing is not required; simply running the bootloader for a few seconds is enough to cause the problem, so it's not due to any code downloaded by the programmer.There seems very little in the CPU which survives an external reset. The RCC registers look the same in each case, and the only difference in RTC registers is the change of time and next scheduled alarm.Our console serial port is on PA2/3, there was a BlueTooth

Hello everyone! In our system we have a set of subsystem that uses F4/F7 MCUs and one - with STM32H743 MCU. We want to use system CAN bootloader for all of them. Everything seems ok, except STM32H743 device. From AN2606 we know that it starts in bootloader with such FDCAN config: 'Connection bit rate 250 kbit/s', 'Data bit rate 1000 kbit/s', 'FrameFormat = FDCAN_FRAME_FD_BRS'. So, it waits for FD frames. The question is: can we use default CAN (not FD) with 250 kbit/s bitrate to update every subsystem there? Will STM32H7 recieve default frames and work in default  CAN formats?

I followed the steps in this demo workshop to upload a simple program to toggle LEDs to the Nucleo-N657X0 board. The project is in FSBL. I can run the code in debug mode and upload the signed program to the external flash on the Nucleo-N657X0 board with STM32CubeProgrammer. However, when I tried to run the code with the 'Run after programming' option, I got the warning that the core is locked up. Besides, the Option Byte tab and the Erase tab are gone when the ST-Link is connected (See figure below), so the commonly suggested fix of modifying Option Byte is not possible..  My board is NUN657X0Q$CR1 (MB1940). I'm using STM32CubeProgrammer v2.20.0. The CubeIDE is v1.19.0. The firmware is STM32Cube FW_N6 V1.2.0. The SigningTool is v2.20.0 as the programmer.  I wonder if there a register that I can check to see the state of the MCU

Hi,I have an STM32g473 with 120kb or RAM, running at 169,75MHz.I have some image data stored starting at 0x2000_0000 which comprise of a palette of 235 colors in 00rrggbb format (1 word per color), follower by 304 lines of 370 pixels (one byte each, which is used as an index in the palette to get RGB value.)The data are copied in RAM to avoid wait states when loading them from flash, which mean most is in SRAM1 but the last 85 lines are in SRAM2 and MCC SRAM. The code is in flash.The first line of data display correctly, but the last 85 lines get one extra cycle per pixel (most probably due to reading the data).I could not find anything in the RM0440 that explains where this one cycle penalty come from. The only peripheral I use in addition to SRAMs and Flash (for the code) are the DACs and one GPIO (the gpio is not accessed during the loop that sends the pixels and get the penalties)Can someone help understanding this?

I'm referring to RM0481 Rev 4 and I'm currently working on my SDMMC driver. For one reason and another, I need to start a data transfer for multiple read/write commands, but without sending the command again (because it has already been done so).The RM states this about the DTEN (Data Transfer Enable) bit: Ok. Maybe I'm missing something, but isn't the whole point of SDMMC is to communicate with SD, SDIO, and eMMC cards? The marketing people said so:

HI, I have a strange issue with our STM32H747 board using the IS42S16400J SDRAM chip.We have been reading the "How to set up the FMC peripheral to interface with... - STMicroelectronics Community" page and this all seems OK.The differences between the system described and our board is that we have 8 MB RAM instead of 32 MB and we do not use the byte lane select signals (LDQM and UDQM from the SDRAM chip are routed to ground). When writing to SDRAM, we see (random) writes to the other 32 bits word within the same 64 bits. This is true for both 16 and 32 bits write from the CM7 core. So writing 0x12345678 to address 0 in the SDRAM results in a random value being written to address 4. Same applies when writing to address 4 - there I see a random value appearing at address 0. If I first write 0x12345678 t

I'm trying to establish communication with FDCAN and view the signal via PCan View, but nothing appears on the screen. There are no errors in the connections. These are the codes: /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file : main.c * @brief : Main program body ****************************************************************************** * @attention * * Copyright (c) 2026 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" /* Private i

I use STM32F407 with internal PHY What external elements need I for connecting USB flash to MCU? 

Post Edited by ST moderator to apply source code formatting to comply with the community rule: I wonder if any one can help me.The rtc Cal freq produced by the init code below produces on 490Hz.  The RTC clock is loosing about 55 sec in 20 minutes.Is there a way to increase this freq without replacing the crystal?     static void MX_RTC_Init(void) { /* USER CODE BEGIN RTC_Init 0 */ /* USER CODE END RTC_Init 0 */ RTC_TimeTypeDef sTime = {0}; RTC_DateTypeDef sDate = {0}; /* USER CODE BEGIN RTC_Init 1 */ /* USER CODE END RTC_Init 1 */ /** Initialize R

I’m using an STM32F439VIT6 on a custom board. PA5 is used as the DAC output, and PA0/PA1 as the ADC inputs. On 1 out of 5 boards, the ADC and DAC functions stopped working, but the same pins still work correctly as GPIO.Setup (failing board)PA5: DAC → op-amp → 0–10 V outputPA0, PA1: ADC inputs from INA190A1 for 4–20 mA sensorsVDDA/VREF+ = 3.3 V (measured OK)Same firmware as working boardsPins configured in analog modeIssueDAC produces no valid analog output, always zeroADC readings are invalid or stuckGPIO input/output on the same pins worksQuestionCan the STM32F4 analog (ADC/DAC) circuitry be damaged while the GPIO still works on the same pins?How can I confirm if the ADC/DAC core is damaged (e.g., internal channels/tests)

Hi all,I am using an STM32H5 micro. I need to send out a buffer of data at regular intervals. I use TIM15 to trigger the GPDMA which sends blocks of 6 bytes to the SPI. The SPI is programmed with TSIZE=6 to get the SS output low during the transmission. I absolutely need this. The screenshot below is the result from my code.My problem is that the SPI only works ONCE. It seems to be stuck afterwards, I observe that CSTART of the SPI goes to 0. How can I get the SPI going on with TSIZE > 0 ?

STM32F4 is working in USB Device MSC mode successfully.I need to detect the USB connection state. I put the HAL_PCD_ConnectCallback function in main.c but on compiling I received warning.Debug/../USB_DEVICE/Target/usbd_conf.c:307: multiple definition of `HAL_PCD_ConnectCallback';I see it is weak in HAL_PCB_IRQHandler. Please suggest what I am missing.   

Hello...I wish to setup ADC oversampler but seems that i really dont understand if its capable to do what i want. this is what i wish to got: ADC triggeredSample adc0, 1 of 4 in oversamplerSample adc1, 1 of 4 in oversamplerADC triggeredSample adc0, 2 of 4 in oversamplerSample adc1, 2 of 4 in oversamplerADC triggeredSample adc0, 3 of 4 in oversamplerSample adc1, 3 of 4 in oversamplerADC triggeredSample adc0, 4 of 4 in oversampler -> result to dmaSample adc1, 4 of 4 in oversampler -> result to dmanext loop:ADC triggeredSample adc0, 1 of 4 in oversamplerSample adc1, 1 of 4 in oversamplerADC triggeredSample adc0, 2 of 4 in oversamplerSample adc1, 2 of 4 in oversamplerADC triggeredSample adc0, 3 of 4 in oversamplerSample adc1, 3 of 4 in oversamplerADC triggeredSample adc0, 4 of 4 in overs

Hello, I'm trying to run SDRAM (AS4C4M16SA-5TCN) with FMC. It looks like all connections are correct. When I try to read/write to memory pointer, I got memory management fault handler.My FMC configuration:Clock connected to FMC is 275MHz (HCLK3). I've tried also to lower it to ~30MHz, but it didn't help.Under "USER CODE BEGIN 2" I'm executing FMC_Init() function. This is it:

Hi everyone,I’m trying to design my first PCB using STM32F103 and I’m still a beginner.I see that the PAx pins (PA0–PA15) have multiple alternate functions like GPIO, ADC, USART, SPI, etc.I’m a bit confused about how to properly choose which PA pins to use for my peripherals.If I use PA9/PA10 for USART, can I still use them as normal GPIO later?What is functionality of PAx pins ?I'm using STM32F103C8T6stm32f103c8 datasheet stm32f103c8t6 I'd really appreciate some guidance before I finalize my board layout.Thanks! Best Regards !

Hello everyone!   I got the following problem; I need to read from two 32bit addresses and write the data to three. Specifically, i am interested in the case shown in the left side of the image, where the N[0:15] increment by half word and write to the M[0:15] but it will increment by a full word. Don't worry about the reserved bytes in the HTIMx_CC1R, I checked the manual and are always at zero.  I saw that the H7 can read/write with weird patters using the fifo functionality. The thing is I can't understand at all how to set it up. Is there any other better way?   Thanks in advance!  

Hello ST Community Team, We are currently working with the STM32N657X0H3Q1 device and using an external DRAM – S80KS5123GABHB020 (512 Mbit) connected via the XSPI interface. We have successfully configured XSPI and external memory initialization (using CubeMX / HAL), and the external memory is intended to be used for TouchGFX frame buffers and application data. However, we would like clarification on the following points: What is the correct memory-mapped base address that should be used for the S80KS5123GABHB020 DSRAM on STM32N657X0H3Q1 ? Is the memory accessed through the XSPI1  memory-mapped region, and what is the exact address range? Are there any STM32N6-specific constraints or alignment requirements when using large external DSRAM (512 Mbit) for TouchGFX or heap al

Hello everyone, I have a Python app that needs to communicate with my custom STM32L432KC board. Before ordering my prototype board, I was wondering if it is possible to do it only via USB with the pins PA11 and PA12, or if I need a USB‑UART chip like the CP2101‑GM?   Thanks

Isn't TrustZone something which started to be only since Cortex-M33?JW

ST moderator: Edited the tile to add "ADC" I want to extract data at high sampling frequency ~10KHz at STM32N6570-DK, Is it possible with USART for three channels or we have any other mode for this purpose. I want to continuously stream data at 10KHz sampling frequency.

Hi, I am struggling with TIM2 to restart its CNT from zero without using hal. I am using nucleo-f446 TIM2 clock frequency is 21MHz (no prescaler, 1/4clock division) CNT set for upcounting. I want to use TIM2 to write a simple us_delay function, so I need to restart its CNT  whenever us_delay is called. No matter what I do, I can't make it work, here is the code I am using: TMR2_Start = 1; //start counter TMR2_URS = 1; //Only counter overflow/underflow sets UIF bit TMR2_UDIS = 1; //disable update event generation TIM2->ARR = 2100; //set 100us delay (tim2 clock frequency = 21MHz) TMR2_UDIS = 0; //enable update event generation TMR2_UG = 0x1; //restart counter while (TMR2_UIF == 0){ //wait until TMR2_UIF is set } I put a breakpoint right before while loop is executed, I can see that CNT is enabled, URS set, de