STM32 MCUs Products

Hello everyone, I’m working on a project to interface an OV5640 camera module with an STM32H743 MCU via the DCMI interface. I’ve set up the STM32H743 in CubeMX and generated a basic project, but I’m looking for supporting documents, example projects, or reference drivers to help with the integration. Specifically, I am looking for guidance on: OV5640 initialization sequence (XCLK, SCCB/I2C configuration, reset/power-down sequence) Recommended CubeMX DCMI + DMA settings for QVGA RGB565 capture Memory placement for DMA frame buffers (AXI SRAM vs DTCM vs SDRAM) Minimal working register tables to enable QVGA or VGA output Any ST or community examples of STM32H7 + OV5640 projects   I understand DCMI + DMA basics, but I am aware that OV5640 requires stricter timing and more complex initialization. Any pointers to example projects, application notes, or reference drivers would be extremely helpful.  

Hello everyone,MCU in use: STM32H745XI (dual-core, Bootloader v9.1, CubeIDE 1.16.1, HAL v1.11.3, CubeProgrammer v2.17.0)Hardware status: BOOT0 HIGH works perfectly, I can access the system bootloader over USART1 (PA9/PA10), and program via UART. Hardware is validated and all connections are good. PB15/PB14 pins are floating, not connected anywhere.My need:I want to jump from user application (C code only, no BOOT0 pin) to the internal ROM system bootloader for firmware update purposes, so that I can upload new firmware over UART (using CubeProgrammer or similar), and then return to normal application on the next reset.Here are the methods I have tried (none worked):Set MSP to 0x1FF09800, jump to 0x1FF09804 (function pointer), disable all interrupts (NVIC->ICER), set PRIMASK/FAULTMASK, disable and invalidate caches (SCB), disab

In section 19.6.2 LCD frame control register (LCD_FCR) of the STM32U0 RM0503 Reference Manual, the examples provided for PS and DIV initially count up in decimal, but finish in binary. This looks like an accident and is confusing to the reader. https://www.st.com/resource/en/reference_manual/rm0503-stm32u0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdfAll other examples further d

I am using stm32l552zetxq. I am testing standbymode with wakeup from event. According to reference manual RM0438, there are 5 wake up pin to wake up the mcu from standby/shutdown mode wkup1 to 5 with polarity setting option in PWR_CR3 and PWR_CR4. But i could not find whic are those 5 pins in datasheet and in reference manual. By searching i find that PA0,PC13,PE6,PA2,PC5 in a documents ""en.STM32L5-System-Power_control_PWR.pdf" in page no 40. Now my question is what is the wkup no of which pin. It should be mentioned either in data sheet or in reference manual. It be very help full to me kindly provide the document with page no or article number and te documents.

Dear all,I'm trying to generate a waveform using DAC OUT1.I configured pin PA4 as analog (works)I configured DAC1 without DMA and it worksI configured TIM6 and it works Then I configured DAC with DMA, configured DMA, but output never changes.Where can I check? I enclose the minimun configuration code: /* DAC Configuration */ if(!(RCC->APB1ENR & RCC_APB1ENR_DAC1EN)) RCC->APB1ENR |= RCC_APB1ENR_DAC1EN; // Enable DAC clock DAC1->CR |= DAC_CR_DMAEN1 | DAC_CR_MAMP1_3 | DAC_CR_EN1; // DMA1 enable | Amplitude 511 |Wave generation disabled | Timer6 TRGO event | Trigger enable | Buffer enable | DAC1_OUT1 enable /* DAC Timer */ if(!(RCC->APB1ENR & RCC_APB1ENR_TIM6EN

Hello,I may have made a *** of myself on a prototype, and need a bit of help with a work-around. I have an external clock signal on TIM20_ETR (PG5) for some pulse counting stuff. This works.However, I intended to use the same clock signal to trigger TIM2 one-pulse (and later TIM5 one-pulse as well), and thought that I could use tim_trgo from TIM20 to clock them. My problem is that, now I have the prototype PCBs in hand, I cannot figure out how to pass the TIM20_ETR clock signal on to tim_trgo – or if it is even possible.My best guess is that I can set TIM20_CR2 MMS to 0010 (Update), and set PSC and ARR to 0. I have already set TIM20_SMCR to use TIM20_ETR as the trigger source. If I understand the timer functionality correctly, this should give me an update event for each clock pulse.This work-around will make me lose the TIM20 counter feature, but if I can just get the external trigger signal out on tim_trgo, then I can use that to clock TIM1 or

Hi,i am using STM32G0B1KB and the UCPD peripherals to implement an USB-PD device with 2 ports:- Port 1 is DRP- Port 2 is Source onlyI need the dead battery pulldowns for port 1, so I will connect the UCPD1_DBCCx pins with the UCPD1_CCx pins as described in the manual. However, for port 2 I don't need to present the dead battery pull-downs - when the MCU is unpowered (dead battery) and the user connects some other device (e.g. smartphone) to port 2, simply nothing should happen. The manual states:> If dead battery behavior is not required (for example for source only products), then UCPDx_DBCC1 and UCPDx_DBCC2 pins must both be tied to ground.What resistance can be used to connect those pins to ground? Since I don't have any pins left, can I instead use the DBCC pins for something entirely different? E.g. connect LEDs (to GND) or some other digital output with a weak external pull-down resistor (e.g. 10kOhm)? Will this prevent the MCU from

Board: NUCLEO-N657X0-QRevision: CProblem: MCU cannot pull PA2 to low, only to about 2.5V. I tried it in push-pull and open drain modes. SB6 has been desoldered to isolate it from the analog attenuation circuit, but it didn't work with it soldered. It doesn't work with the "GPIO_IOToggle" example project either, same behaviour. Pulling the pin up to 3V3 works just fine. PA2 is the pin so far which has caused this issue. Holding the reset button makes the pin go high (3V3), indicating a hardware issue, as far as I know. My best guess is it is somehow pulled up through a pull up resistor, but I haven't found any evidence of it in the documentation.I attached some documentation which I investigated.Any help is appreciated, thank you!

Hello,I have an STM32G441 and using DMA to transmit some SPI data. All works so far. The problem is the chipselect. I am using the software chipselect. So before I start the DMA I pull CS low. Then when the DMA complete interrupt fires I pull it high again. The problem is, it cuts off about 3 or 4 bytes. This is obvious because the DMA is done while there is still SPI data in the buffer. What is the go-to solution for this? How can I reliably get an interrupt when the DMA is done and the SPI is done transmitting all data? At the moment I simply start a timer when the DMA is done that triggers a second interrupt after a certain time that I measure with a logic analyzer. Seems a bit makeshift and has to be adjusted each time the baudrate is changed. I also noticed that all the SPI interrupts fire premature. So is it the only solution to waste a timer on the SPI?

Hi,How to set UID using CubeMX and read in STM32L476 and use it for device commissioning process?

I am currently using an STM32L011F4U6 to communicate with some other chips and it is failing to pull either I2C line down to GND fully when signalling, they are seemingly clamped to approximately 1.2V at a minimum as shown below making it impossible to communicate with my I2C devices which need the I2C lines to drop below 0.5 V to register a low state. Is this something anyone else has dealt with?I2C waveforms with 10k pullups at Normal Mode speedsI am using PA9 for SCL, PA10 for

Hello,I am currently reviewing a hardware design based on the STM32H563ZIT6 and have some questions regarding the internal and external behavior of the NRST pin.My main question is how the NRST pin operates specifically during an NVIC_SystemReset.Currently, we are using an external pull-up resistor (connected to 3.3V) on the NRST pin.According to the Datasheet (DS) and Reference Manual (RM), I confirmed that the NRST pin has an internal weak pull-up (RPU), which is typically 40 kΩ.

Hi.I created code and flash memory that is already 80% used. Is that okay? Will it affect performance?Thank you:)

May I ask how the FDCAN Message RAM offset allocation,  Tx and Rx BufferElementSize can be configured on G4 Series. As in cubeMX it doesnt give me the option to like the H7 series. Or is that done automatically by the core when generating the code?If so, could I know if it is possible to change it? 

Hi,I have a strange problem on an STM32L051C8 with the comparators enabled in window mode.If I put the system in stop about 20 seconds after powering the microcontroller, the current draw is about 250 uA. If I then exit the stop mode with a soft reset and put the system back to stop after 20 seconds (without removing the power), the current draw is 0.42 uA.The comparator is initialized in ultra_low_power mode with interrupt enabled to exit the stop mode.What can I look at?Thanks

Could you please help me find out how much internal storage space this model STM32F427VIT6 has? Thanks a lot.

We are currently working on a project using the STM32H750IBT6 microcontroller interfaced with a single-bank Quad SPI NOR Flash (MT25QL512ABB) on our custom board. The QSPI interface is operational.However, we are facing an issue with the external loader. While the same external loader setup works correctly with the STM32H750 development board using the same two MT25QL512ABB Flash memories, it fails to function on our custom board.Development board QSPI schematic: Our custom board QSPI schematic:

I noticed some options in the CUBE IDE for my H745's ADCs labelled "ADC 12-bit optimized resolution" and likewise for 14 bits. I have searched the references and the internet and find no explanation of how "optimized resolution" differs from the regular resolution. Does anyone know what this means, and where it is documented? Thanks 

I am using the USB OTG FS on the STM32H7. My MCU is self powered, so I need to use VBUS sensing. Can a 3.3V signal be used for the VBUS sensing on PA9 or must it be 5V? Based on the linked forum, I believe 3.3V would work, but would like to confirm with the STM32H7 series.https://community.st.com/t5/stm32-mcus/management-of-vbus-sensing-for-usb-device-design/ta-p/49485#:~:text=On%20STM32F2/F4/F7/,136): How should I configure OTG_FS_ID PA10 so my MCU is device only? Should I leave it floating, pulled to LOW, or pulled HIGH?   Thanks in advance for any help on this topic.

Hi All,Please could somebody offer some words of wisdom to resolve the apparent ambiguity in the C0 datasheet, which on the one hand states that once IWDG is started it cannot be stopped, yet on the other hand offers a IWDG_STDBY bit in the OPTION registers to allow it to be stopped during Standby. The latter does not appear to work, since my system wakes itself after the prescribed watchdog period, so it seems like the first statement is the correct one.Since the watchdog definitely CAN be stopped during debug if DBG_IWDG_STOP is set, there is clearly a mechanism by which it can be stopped under certain circumstances, suggesting the first statement is not correct, or at best is not the whole story.If it can't be stopped in Standby....a) what's the point of the IWDG_STDBY bit?b) how can I keep my system in Standby? I must have the watchdog running while awake.&nb

Hello,I stumbled over a weird problem when trying to debug Memory Protection Unit (MPU) settings which I want to document here in case any other people have the same issue:SetupThe used MCU is a STM32H7S3L8H6 on a STM32H7Rx/7Sx Nucleo-144 board (MB1737)Core frequency is 400 MHz.Enabling or disabling the cache has no impact on the problem.The code is executed from the internal flash, the stack and variables are placed on the DTCM.The debugger which I use is a Lauterbach CombiProbe 2 attached to a Power Debug Pro Ethernet. TRACE32 PowerView software version is R.2025.09.000186004.The executed software is a custom operating system which uses the MPU to prevent user-space threads from accessing memory regions not allocated to the threads. For this, one MPU region each is used for ROM, RAM and stack. The MPU is activated before the th

Hai All!I use 2 pieces of APS25608N PSRAM on OSPI bus with memory mapped mode. The MCU run at 1.8V, 160MHz system clock. Previously, I used APS12808N at 80MHz and 3.3V VDD without any issues.Currently, the PSRAMs run at 50MHz, but need to speed up to 100 or 160MHz.I thought the aps256's default settings should be good up to 100MHz, but they weren't.My working settings at 50MHz was ( relevant source in attachment): MR0: Fix type latency, latency code 5, and full strength (25 ohms).MR8: 32Byte Warp burst and without crossing.OSPI settings are:Dummy cycles:  Read = 8, Write = 4 hospi->Init.FifoThreshold = 4; hospi->Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE; hospi->Init.MemoryType = HAL_OSPI_MEMTYPE_APMEMORY; hospi->Init.DeviceSize = 25; hospi->Init.ChipSelectHighTime = 2; hospi->Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE; h

Hello everyone. I am trying to write a bootloader with STM32H750IBT6 and mt25ql512. I am trying to adapt the ExtMem_Boot example of STM32H750-DK to STM32H750IBT6 by modifying it, but I can't succeed. It doesn't make sense why STM32H750IBT6 does not work. In the software; JumpToApplication = (pFunction) (*(__IO uint32_t*) (APPLICATION_ADDRESS + 4)); __set_MSP(*(__IO uint32_t*) APPLICATION_ADDRESS); JumpToApplication(); but JumpToApplication(); enters HardFault and I get SCB->CFSR = 1025. Whatever I did, I was not successful. Attached I share the bootloader and application projects.

Hey guys, I'm looking for some suitable HexaSPI PSRAM and also the OctoSPI Flash for the STM32N645 board I am just building.. I cant find the parts used on the DK so do you have a list of supported memories? I need 256Mb PSRAM and will start with a 1Gb Flash as per the DK..  Richard

Hello, I am planning to use the STM32G474RET6 and would like to confirm whether I can use the internal VREFBUF. This product's package is LQFP-64 and while reading the datasheet I noticed the note : ''The VREF+ pin is double-bonded with VDDA on some packages''. Could you verify whether the internal reference voltage can be used with this package?   Thanks.