STM32 MCUs Products

My original aim was to prove to myself that I was able to measure execution time with cycle accuracy. In order to do that, I have 9 'test_dwt' functions, they all have same code except number of nop between 2 reads of DWT.That gives unexpected results because M55 has dual-issue capability, as people explained here. Nevertheless, I am puzzled with the result of test_dwt7 (7 nops). All clocks are at 100MHz, interrupts, icache and dcache are disabled, all 'test_dwt' functions starts with isb and dsb instructions.Here I print the result of 5 executions of each function. The execution order is 0 to 7c, repeated 5 times, saving results in an array. Then I print the results:test_dwt0 : 1 1 1 1 1 test_dwt1 : 1 1 1 1 1 test_dwt2 : 1 1 1 1 1 test_dwt3 : 2 2 2 2 2

Hello ST Community,I am working on an OTA firmware update implementation on STM32L496, and I am facing an issue related to dual-bank internal flash usage when the firmware size exceeds 512 KB.I would like to explain my setup and the problem in a simple and clear way. MCU and Flash DetailsMCU: STM32L496Internal Flash: 1 MBFlash configured in dual-bank modeBank1: 512 KBBank2: 512 KB What We Are DoingNormal ApplicationThe main application is stored in internal flashFirmware is built using STM32CubeIDENo OTA activity during normal operationOTA (Current / Tested)OTA is performed using

the best I achieve so far using DWT as well as PMU is 'few cycles' accuracy. My question is, how I measure execution time such that I get 1 cycle difference when I insert a nop in the measured code ? (assuming interrupts and caches are disabled).Both functions below return 1!.global test_pmu0 .type test_pmu0, %function .align 2 test_pmu0: isb sy dsb sy ldr r3, .test_pmu0.pmu_base ldr r0, [r3, #0x7C] //read PMU->CCNTR ldr r1, [r3, #0x7C] //read PMU->CCNTR sub r0,r1,r0 bx lr .align 2 .test_pmu0.pmu_base: .word 0xE0003000 //PMU base address .global test_pmu1 .type test_pmu1, %function .align 2 test_pmu1: isb sy dsb sy ldr r3, .test_pmu1.pmu_base ldr r0, [r3, #0x7C] //read PMU->CCNTR nop ldr r1, [r3, #0x7C] //read PMU->CCNTR sub r0,r1,r0 bx lr .align 2 .test_pmu1.pmu_base: .word 0xE0003000 //PMU base address 

I have a custom PCB with an STM32H563VGT6 microcontroller and an external Winbond W25Q16JVUXIQ NOR flash memory connected to the octoSPI's (XSPI) upper four pins. The problem is I can only write data to the flash memory after an erase, if I reset my board between the two operation. Everything the erasing, writing, indirect reading, memory mapped reading work on their own, but not after erase without reset. I read out all 3 status registers, they are the same before and after the chip erase. (Of course I set the write enable bit before trying to write into the memory) Any idea what could be the problem?

I want to design a baord with stm32h7b0zbt6 with extranal sdram chip W9825G6KH-6. I get PG15 with FMC_SDNCAS alt func in datasheet as below:But when I looked the PG15 alt func config I get as below info, I could not found an alternate function number for FMC_SDNCAS here ?? why they are not consistent ?

Hello,Description: I am attempting to generate two simultaneous pulses of different lengths using a single timer (TIM4) and multiple channels.Current Implementation: I am currently using One-Pulse Mode (OPM). In my existing setup, the pulse starts at CCR and ends at ARR. However, since ARR is a global register for the timer, all channels are constrained to the same end time, making it impossible to achieve independent pulse widths if they all trigger at the same ARR event.Objective: To achieve independent pulse widths, I want the pulse to start at CNT = 0 and end at CNT =

I am trying to get the CAN Loopback up and running on my STM32L431KCU (CAN1), I have tried to follow the: Guide to CAN (bxCAN/CAN2.0) configuration in Loop back mode on STM32 MCUs. But I am getting stuck in the "HAL_CAN_Start()" function where its waiting for the acknowledgement:  /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; return HAL_ERROR; } } I then created a new project following the CAN loopback project listed here to get a working project and around my issue: 

Hello,here the exit of my (extended)initialization prodecure for ADC of STM32U535 running at 3.3v and 160 Mhz.  Before setting ADC_CR_ADSTART, without the small delay or with the delay in line 14  and the limit for i smaller "6" like here "5" in the code, ADC_CR_ADSTART stays high  and the programm keeps in the while (ADC1->CR & ADC_CR_ADSTART)  loop line16/17. __DMB() is not replacement for the delay.Is the needed delay some artefact of my setup or some requirement that I do not find/oversee in RM0456? ADC1->CR |= ADC_CR_ADCAL; /*8*/ while (ADC1->CR & ADC_CR_ADCAL) { __NOP(); } __DMB(); ADC1->CR &= ~ADC_CR_ADCALLIN; __DMB(); const uint8_t channel = 19U; AdcSetRegularSequence(ADC1, 1U, &channel); ADC1->CR |= ADC_CR_ADEN; while (!(ADC1->ISR & ADC_ISR_ADRDY)) { __NOP(); } for (volatile int i = 0; i < 5; i++) {} ADC1->CR |= ADC_CR_ADSTART;

Hello all,We are testing LPUART wake-up from Stop 2 mode using the STM32CubeU0 LL example:STM32Cube_FW_U0_V1.2.0/Projects/NUCLEOU083RC/Examples_LL/LPUART/LPUART_WakeUpFromStop2_InitWe made a minimal modification to the example:Replaced LPUART1 with LPUART2 Used the corresponding GPIO pins for LPUART2 (PB10,PB11)Configuration otherwise unchanged (same clock source, wake-up on RX, interrupt-based RX)Observed behavior on NUCLEO-U083RCAfter programming the board using STM32CubeProgrammer in hardware reset mode, the example works correctly:MCU enters Stop 2RX activity on LPUART2 wakes the system as expectedHowever, after disconnecting and reconnecting the power supply LPUART2

For the microcontroller STM32H562IIT6, does it support code execution from External flash(Xip)? Also does it support Quadspi interfacing in given Octospi lines?

Is the flash dual-BANK feature of H563 enabled by default? How to switch banks

Hello,I was trying to implement extended calibration for ADC1 on my STM32U575 according to RM0456 Rev 5.  I have a revision ID 0x3001 chip which should support extended calibration.  The chip would hang very badly (can no longer connect with debug probe!) after step 6 ("Set the LATCH_COEF bit").  I took a look at the HAL code in stm32u5xx_hal_adc_ex.c  and it is doing a few things differently:Using DMB instructions between setting CALINDEX and CALFACT and between setting CALFACT and setting LATCH_COEF.Preserving the low-order 8 bits of CALFACT when writing 0x03021100 to the register.When I changed my code to do those two things the ADC now completes calibration properly and doesn't hang my debug connection.It woul

hiim trying to design ADC module with STM32L452.in datasheet table 77, t_s must be 0.03125us - 8.00625us when f_ADC is 80MHzbut in table 78 the range of sampling time is 32.25ns - 8006.75ns.isnt it must be 8006.25ns?

Can the STM32G031Y8Y6TR be subjected to ultrasonic cleaning after being mounted on the board? Are there any internal structures that do not allow ultrasonic cleaning?1. **Cleaning agents**: ST-240KKA or pure water2. **Temperature**: 55°C or below3.**Duration**:Within 6 minutes4.**When using ultrasonic cleaning**:*Frequency: less than 45 kHz

Hi all,In my project I use several IOs, I2C, SPI, UART, ADC, DAC and most of them work as expected.However, I have 2 inputs from push buttons (pushing the button would set them to 0 volt), set with pull-ups (not set as EXTI) that sometimes stop working after a while: When I check the voltage I see the level is changing, but when reading these IOs using HAL_GPIO_ReadPin() their state doesn't change anymore until I reset the PCB.The rest of the software still works fine when it happens.Never seen this before on ST, and this project was actually migrated from STM32L031 which never showed the issue. I'm having a hard time reproducing the bug, it seems very random so far.If I called the GPIO Init on a regular basis, would it prevent this issue?Kind regardsP.S: I use GNU tools for STM32 v13.3.rel1

The VENC peripheral on the N6 boasts a hardware handshake path with the DCMIPP peripheral, potentially allowing full compression of each frame to occur with very little active RAM. From what I can find, the DCMIPP capture starts, then the VENC is told to start encoding, and the application only then receives notifications when a frame is complete. There should be no further interaction. However, I am unable to get this working for MJPEG. The examples for this sort of streaming are all for h264, and the JPEG is thrown to the side as a one-time encoding. I have reasons on this project to use MJPEG encoding, but I cannot get the VENC to perform this handshake with the supplied example code. I have attempted to modify the JPEG Encoding Example that uses the VENC, and have successfully used the VENC for JPEG encoding of a full in-RAM frame, so I know the peripheral can work. Relatedly, the only articles on the handshake algorithm I can find is for the H264 compression.I'm looking

In the UM2407 Rev 5 (Nucleo-H753ZI user manual) on page 29/54, section 7.6.6 there is a warning:USB Micro-AB connector (CN13) cannot power the Nucleo144 board. To avoid damaging the STM32H7, it is mandatory to power the Nucleo-144 before connecting a USB cable on CN13. Otherwise, there is a risk of current injection on STM32H7 I/Os. However, in an informal empirical test it seems that nothing got damaged when I connected CN13 to a PC/Laptop without powering the Nucleo. So, how big is this "Risk" really and what are potential consequences? And is this risk related to the Nucleo only, or would the same risk apply when integrating a STMH753ZI directly on a PCB. Can anybody provide more detailed information?Note: I do NOT want to power the Nucleo from CN13 but just leave the USB cable connected. Thank you and best regardsDiego 

Hello,we are seeing a systematic offset when using the internal temperature sensor of the STM32G031G8U6.Over the years we have tested ~50 SoCs (different production batches), and all devices show a very consistent temperature reading that is about 2–3 °C too high at room temperature compared to an external reference, higher temperatures weren't tested.Because of this, we are considering programming a temperature offset during flashing. Before doing so, we would like to better understand whether a single-point offset calibration is sufficient, or if the internal slope accuracy is not reliable enough, requiring a full two-point calibration.Example:If the MCU reports 24 °C but the real temperature is 21 °C,

Hi everyone,I’m experiencing unexpected behavior while testing 9-bit SPI on an STM32, observed with a logic analyzer. The issue only occurs when the MOSI line is physically connected to the slave.Observations::keycap_1: MOSI not connectedCS and SCLK are correctMOSI stays highSPI decoder shows 0x1FF Expected behavior for a floating MOSI line:keycap_2: MOSI connected to the slaveMOSI data becomes correctBut a very brief rising edge (glitch) appears on CS during data transmissionCS immediately returns active → causes unintended slave deselectionResult: data loss during the SPI frameAdditional info:STM32 model: stm32u5g9j-dk2SPI mode: 9-bit, masterSCLK frequ

Im trying to run SYSCLK from LSI on a STM32C011. But it appears as if the MCU is not running. I cant see anything in the datasheet that says the clock cant be used and it can be routed fine in the clock configurator. Am I missing something in the datasheet or does the HAL not support it?

STM32G031Y8Y6TR  SMT上板后 需超声波清洗 PCBA 满足MOB制程需求，清洗参数：40KHZ，6分钟，60°，有经验的大神协助回复下1.STM32G031Y8Y6TR 是否禁止超声波清洗元件2.超声波清洗参数建议多少

I am using STM32F767 with LWIP and LAN8742 PHY.Ethernet initializes but I am facing Ping does not work reliably. This is the Schematic.

Hi,I’m developing an application on multiple STM32H563 units on the same board. Although all units use the same firmware, the logic depends on each unit’s position, so I need a way to identify which unit it is.Currently, I program the full flash memory (.bin/.elf) with STM32CubeIDE or STM32CubeProgrammer. Is there a standard or recommended way on STM32H563 to store small per-device information (like unit ID or role) separately from the main application flash, so the firmware can read it at startup? Thanks for any guidance!

Hi All, In datasheet of STM32N657X0H3Q controller only power-up sequencing details are shown., Is there any power down sequencing is required?If Yes, Please suggest the document which gives complete information of power down sequencing. 

Introduction: While testing the U575 with external PSRAM connected over OCTOSPI1, certain memory test scenarios fail deterministically.   Setup: Using a STM32U575, connected on OCTO-SPI1 to PSRAM (IS66WVH8M8) 8MB in size. The STM is configured in memory mapped mode, hyperbus enabled, no DMA or Cache enabled, & wrap/burst mode disabled.   While testing the PSRAM using Barr tests, found that the data bus and address bus test pass, but the device test had a determini