STM32 MCUs Products

Hi everyone,I’m using an STM32L562 MCU and outputting LSE (32.768 kHz) to MCO for measurement.In LSE crystal mode, I see a large frequency deviation on the oscilloscope (much larger than expected ppm-level error).To rule out the crystal itself, I checked the 32.768 kHz crystal and it seems OK.Then I tried LSE bypass mode (feeding an external 32.768 kHz clock into the LSE pins). In this case, the MCO output frequency error becomes very small, and the waveform/frequency looks correct.So I suspect there might be an issue with the LSE oscillator circuit (load caps, PCB layout, drive strength, leakage, etc.) when running in crystal mode.Questions:Has anyone experienced large LSE frequency error in crystal mode on STM32L562 / STM32L5 series?Any common

Hey,  I am using the STM32G0B0VET (16MHz HSE) with a virtual com port over USB. The virtual com port is working fine but as a backup I would love to be able to let the user reflash the device. I was thinking of using the DFU for this since then the user would only need a standard USB cable (consumer electronics hopefully high volume). I exposed a button that can pull BOOT O high (small reprogram button you have to push). (Normally in the field updates are not needed but I would like to have this as a backup). Now I have the following problem when I boot the device (that is flashed) when pressing the button (keeping BOOT 0 high) my PC sees the virtual COM port and not the DFU device. It is thus running the usual code and not entering the bootloader. If I erase the STM32 with the ST link I can access the DFU just fine with the boot button. Does anybody have a fix for this

Hi,i have  new design that i am migrating to the STM32G071 and having issues with the SPI1 port PB3,PB4,PB5. Changing CPOL and or CPHA during init code do not seem to have any impact, when powered down and restarted.I am seeing 9 clock pulses when set to 8 bit data. Suspect this might be issues with the overall SPI setup.the init code is simple changed to the absolute simplest format.ignoring setting the PB3,4,5 GPIO pins as they are good i can see the signals on the cro// bidirectional mode full 2 lineSPI1->CR1&=~SPI_CR1_BIDIMODE;// set as masterSPI1->CR1|=SPI_CR1_MSTR;// CPOL clock idle lowSPI1->CR1&=~SPI_CR1_CPOL;// CPHA rising clock edgeSPI1->CR1&

If I am correct, the descriptions of - HRTIM_ADC2R   -  Bit 22 - HRTIM_ADC3R   - Bit 19   - Bit 13 - HRTIM_ADC3R   - Bit 22   - Bit 13   - Bit 10   - Bit 5   - Bit 4   - Bit 0are not correct in the RM.They all describe trigger event generation but the trigger output in all these seem wrong:E.g.: HRTIM_ADC2R, Bit 22,Original Text: "This bit enables the generation of an ADC trigger upon timer C reset and roll-over event, on ADC trigger 1 output."It should be: "This bit enables the generation of an ADC trigger upon timer C reset and roll-over event, on ADC trigger 2 output."Also, I want to ask, if this forum is the right place to give feedback on documentation issues?Best Simon

Dear ST Team,I am using an STM32H5 series microcontroller in my design and I am trying to understand the overall power consumption contributed by different MCU interfaces.So far, I have identified the following:The typical maximum current on VDD, in VOS0 condition with all peripherals enabled, at 85 °C, is approximately 118 mA (based on STM32H5 datasheet values).My Question:I tried to find similar information for the VDDIO supply pins.However, the datasheet only provides peripheral-wise consumption in µA/MHz, which appears to apply to low‑power (sleep) modes, not active RUN‑mode.I want to calculate the VDDIO current consumption for my specific design configuration.My active interface

Hi everyone,I am currently trying to measure the CPU temperature using the internal temperature sensor of an STM32F733.I am testing the device inside a climate chamber (oven) to verify the readings. I am fully aware that the datasheet states the sensor is more suitable for detecting temperature variations rather than absolute measurements. However, the values I am getting seem to have a significantly larger offset/gain error than expected.The Setup:MCU: STM32F733Method: To rule out self-heating of the die, the device is kept powered OFF inside the oven until the target ambient temperature is reached and stabilized. I then power it on and immediately take the ADC measurement.Vref+: Connected to external reference voltage (2.048V).The Observations:Oven at

Hello, i am using a stm32f103 mcu to provide rtc functionality. I am using a external crystal  of 32768 hz for the rtc block.The crystal is rated at 6pf load. +/- 20ppm  PN:   QT1C-32.768KDZB-T Apart from this i have also implemented a external gps module   to provide a  "reference time" via uart.Upon power on, the mcu configure the rtc counter with values for  hours,minutes,seconds  taken from the  the gps,   then i just display them on a lcd.My problem is the time drift  on the rtc when comparing the time from the gpsFor example, after 10 hours of functionality,  my  rtc clock drifts with 7-8 seconds when compared with the gps time. I have tried to measure the rtc clock on the tamper pin, and here things start to show upThe measured frequency on the tamper pin ( PC13)    is 512.295hz.

Good Morning,   I'm struggling with FDCAN Bus Recovery. The system we have to use consists of an STM32H753-based board and a 3rd party ECU, which is internally terminated via software. Our custom board is also terminated, resulting in the correct 60 Ohm between CAN Hi & CAN Lo. In the event I add an additional termination resistor to the Bus, the power-up sequence doesn't matter, however the bus is the over-terminated, which is obviously not correct. I can, however, see the custom board initially blurting out a CAN frame as fast as it can before the other ECU has finished powering up, and then normal CAN comms is seen on PCAN (the PCAN has been configured to not send any Acks). However, if I leave the bus as it is, it looks like the bus from the perspective of the custom board just turns off. I can see the 3rd party ECU splurging out one of its' messages as fast as it can, however our board should be seeing this message and transmitting Ac

Hi there,I have been struggling with the PSRAM. I bought the STM32H7S78 board to pick up the know-how to understand how I should configure the PSRAM at XSPI1 via the EXT MEM manager at my own board. My clock speed is 200MHZ XSPI. PSRAM MPN: APS6408L-OBMX-BAMCU type is slightly different (STM32H7R7L8H6)For sure, I connected the programmer to configure the sbs since the VIO is 1.8V. What I missed from the HW was that I forgot to add the pull-up resistor at the CE pin. Note: I desoldered from the original ST board to check the behaviour and did not influence its behaviour. The reset is connected to the NRST by a diode. Note: Checked the connections, footprints. GND is on the mid1 layer and all of the connections are on the top layer. The length is less than 14mm and the distance between the track are usually 0.2~0.25mm.So all in all, I excluded the HW errors. Note: I bought the same PSRAM as on the ST board and I can use th

I have a new board design that interfaces an STM32L4A6 with a uSD card using 1.8V I/O. The SD Card is powered by 3.3V and supports the LVS mode of SD. The STM32L4 does not seem take account the SD specification 6.0. There is no auto detection mecanism of the signalling voltage level in this MCU. This MCU can not start in UHS-I 1.8V mode.Do you know a MCU which can start the LVS identification sequence ?

Is there a comprehensive single documentation source of the Flash layout for say, an STM32H563?The documentation I find is very opaque.  Questions I have at present (From a non secure perspective):1. Where is OBK located? (0x0BF0000 to 0x0BF9FFFF ???)2. Where is system located?3. Is RSSLIB actually using OBK memory? Or is this located somewhere else?4. Is there a way to self program the debug password for PRODUCT_STATE > OPEN?5. If #5 true, are there some real docs on this?  All I find so far is tutorials and code for the 573 in a secure perspective. 

Hello,I want to add a software update feature to my device, but I am unsure about the correct way to verify a newly installed firmware image. My goal is to make sure that the entire firmware has been written correctly and is not corrupted before the bootloader starts using it.One idea I have is to calculate a CRC of the whole application at build time and store this CRC at the end of the application image in flash. Then, during boot, the bootloader would calculate the CRC of the application in flash and compare it with the stored value to decide whether the firmware is valid. However, I am not sure if modifying or reserving a part of the application flash for this purpose is a good or recommended approach.Are there more common or reliable methods to verify a newly installed firmware before activating it? How is this typically handled in bootloader-based firmware update systems?

Hi,I am getting a warning "The core is locked up" and a few more (please refer to the attached image).I have also tried flashing with the hex file, but some flashing issue is observed.

Hello!I am interfacing an ADS131M02 ADC to the STM32C0116-DK board using SPI for a project I am developing on live streamings. I am able to read SPI Data using the HAL polling functions (HAL_SPI_TransmitReceive), however that created unwanted delay between bytes and I tried swithing to DMA to improve performance. Configuration:All clock to max (48MHz)SPI: Full-Duplex Master, 8bits, Mode 01, DMA Tx + DMA RxPrescaler 2: BaudRate 24 MBits/s -> FAILPrescaler 4-Max: SUCCESSThis is the result with prescaler set to 4 (12 Mbits/s). (Pink: MISO, Blue: SCK), the data is correct.

I am working on the NUCLEO-H755ZI-Q, which contains a dual-core STM32H755 (Cortex-M7 + Cortex-M4). I configure the system clocks in CubeMX as follows: SPI1/2/3 Clock MUX: 400 MHz System Clock: Configured for high-speed operation CM7 core frequency: Correctly matches the configured value (e.g., 200 MHz / 400 MHz depending on settings) However, when I debug or read the CM4 core clock, I always see: CM4 clock = 64 MHz It does NOT increase even when I configure higher values in CubeMX.  Regards, Prathiksha

Hy,we are about to create a Proof-of-concept system for a camera application. We want to use STM32N6 Nucleo-144 board (MB1940) Board and add a extension board to CN2, CN3, CN15 and CN16. The project needs Ethernet (which we want to use from Nucleo Board) and PSSI16 Bit (which we want to realize on the extension board).I create a CubeMX project from scratch and select Nucleo Board as starting point.I am not able to configure both, Ethernet and 16 bit PSSI. When I start from the controller itself (no Nucleo) it seems to workWhat do I miss?Best regardsHarald 

Sequent Microsystems designs and sells Automation Systems using Raspberry Pi. All our products use STM processors. We use about 10,000 processors per year in different configurations. Generally we do not have any quality problems, but occasionally we run into a defective lot. On a recent run of 30 prototypes using STM32G431CBT6, 50% were defective. We replaced the processors and all boards worked as expected. We buy all out processors from a Chinese distributor.We saved the defective processors and I would like to know if you would have any interest in inspecting them to find out why they entered the distribution chain, and to advise us how to avoid this problem in the future. Mihai BeffaCEOSequent Microsystems

Bit-banding Alternatives for Modern ARM Cores Background Information: The bit-banding feature available in ARM Cortex-M cores (ARMv7-M architecture including Cortex-M3 and Cortex-M4) provides hardware-level mapping of individual bits within a 1 MB memory region to words in a 32 MB alias region. This mechanism enables atomic bit manipulation without requiring read-modify-write operations.   Specific Query: For ARM Cortex cores beyond M7 architecture that do not support the bit-banding feature, could you please provide detailed information regarding:   Available alternative methods for atomic bit manipulation Performance implications of these alternatives Recommended implementation strategies for maintaining atomic operations Code examples demonstrating these alternative approaches Request for Documentation

I am using a Nucleo-N657X0-Q board to prototype a data collection system that collects samples from an ADC connected to the SAI peripheral and places the results in RAM. If I use CPU AXI RAM0 as the destination this works correctly, but if I change the destination to DTCM all I get is a buffer full of zeroes.According to chapter-17 of the ref manual, HPDMA1 AXI port has access to the DTCM and I am setting the DAP field of HPDMA-CH0 TR1 register to Port-0 as required (setting it wrong results in a DTEF interrupt).I have RISAF 1 and RISAF 2 set as follows: RISAF1->REG[0].CFGR = 0x00000000; RISAF1->REG[0].CIDCFGR = 0x00FF00FF; /* RW for everyone */ RISAF1->REG[0].STARTR = 0; RISAF1->REG[0].ENDR = 0xFFFFFFFF; /* all-encompassing */ RISAF1->REG[0].CFGR = 0x00000101; /* enabled, secure, unprivileged for everyone */ RISAF2->REG[0].CFGR = 0x00000000; RISAF2->REG[0].CIDCFGR = 0x00FF00FF; /* RW for eve

 I am working with an STM32F0 device and I want to implement a firmware update mechanism.My current plan is to split the internal flash into three regions:Bootloader: 0x08000000Application Slot 1 (App1): 0x08004000Application Slot 2 (App2): 0x08008000The bootloader always runs first.Only one application slot is active at a time.The update flow is planned as follows:If App1 is currently running and a new firmware update arrives, the new firmware is written to App2.If App2 is running, the new firmware is written to App1.After the update, the bootloader selects which slot to boot.My concern is about the linker script (.ld) configuration:When I build a new application firmware, I set the flash origin address in the linker script to:  

I am working on an STM32N6 hardware design, and have reviewed both development kit reference designs (MB1939/MB1940). Both designs use the same power supply scheme, when using internal SMPS it has 2x 3V3 regulators and 3x 1V8 regulators.I am interested in combining several power supplies if possible, notably:1. Is it possible to tie all 3V3 together?While AN5967 suggests to apply VDD33USB in the last step of power sequencing, the VDD33USB supply is noted to be independent of the other supplies within the N6, just like the VDDIOx supplies. The reference designs have tied VDDIO4 to VDD at 3.3V, which makes me believe I could also combine VDD33USB and VDD.Aside from just VDD33USB and VDD, all the 3.3V peripherals on the dev kits come from the second 3V3 supply, can I tie all peripheral 3V3 to VDD33USB and VDD, so I have a single 3V3 rail on the PCB?If not what about the STM32N6 disallows this?2. Can I combine 1V8 for p

Experimenting with STM32F427 and STM32F446 I found out, that the RCC_CR.HSEBYP bit is *not* reset by Software reset. It is reset only by NRST and Power-On reset.While applications where this could lead to problems (i.e. where HSE clock source is changed on-the-fly and software after performing Software reset relies on reset state of this bit) are probably very rare, it may result in an "interesting" surprise if one stumbles upon it, and deserves to be documented.Can ST please confirm/explain and document?Thanks,JW

Hello sir/miss , According to the STM32H7 datasheet, the range of the HSE external crystal oscillator is 4M - 48MHz. However, when we used the STM32H7IIT6-EVAL evaluation board and replaced the original 25MHz surface mount passive crystal oscillator with a 48MHz passive crystal oscillator, we were unable to obtain the corresponding 48MHz frequency from the MCO-PA8 pin. Summary: All conventional passive crystals from 4M to 40MHz were tried and worked fine. However, for external passive crystals above 40MHz , just like 48MHz, the MCO output waveform frequency was 16MHz, which is 1/3 of the HSE frequency, and it was unable to output 48MHz. Please provide a solution or suggest areas where we can improve the test. Thank you very much!

Hello I would like to build a full bridge converter according to attached topology picture. The signals for controlling the switches should be like in the picture pwm_scheme. The frequency should be 500KHz. How to configure TIM1 or TIM8 on STM32H725ZGT6 to achieve this? To control the current i1 with lowering the duty cycle of the PWM which input is better to use: ETR or BKIN? Best regards Simon

Hello Community,We are currently evaluating the STM32H562IGT6 microcontroller for our development project. During our review of the device’s pinout, we observed that several GPIO pins are designated as FT (5‑V tolerant). We would like to request clarification regarding the electrical behavior and long‑term reliability of these pins when subjected to a continuous 5 V digital input.Specifically, we would like to understand whether applying a constant 5 V signal to the FT‑labeled pins may have any impact on product lifetime, derating considerations, or long‑term performance degradation.The following pins are of particular interest for this inquiry:PC0FT_aPC1FT_ahPA0FT_atPA6FT_ahPA7FT_ahPC4FT_a