STM32 MCUs Products

Hi, I have stm32l4ri-eval how do i configure the octospi interface to use the issi hyperam which is onboard.

Hello I am having an weird issue and was hoping if someone could provide some guidance. Hardware : Two Stm32 H7 with CAN Transciever Nvidia Orin Can Adapter/Sniffer (Canable) What works :  Stm32H7 to Stm32H7 Nucleo Board Can Bus works. Nviia Orin < - > Canable Adapter Can bus works. Issue : Can bus communication from stm32 H7 to Canable Adapter are not coming through. neither Tx nor Rx. What have i done to troubleshoot Checked wirings for High to High and Low to Low and Tx and Rx as well. Checked voltages for Rx pins at 3.3v( using level shifters wit h transciever) Checked termination resistance and have tested the connections in isolation with both ends terminated with 120ohms ie (stm32- > stm32, Stm32-> adapter, Stm32 -> Orin) I have tested with different baud baud rate like 250, 444, 450, 440, 5

Hi guys i have a nucleo h7A3Zi-q dev board . i am trying to receive CAN messges sent from ESP32 borads . esp is sending can  frame by using SN65HVD232D. and i configured the FDCAN to receive the can messages . esp can is set at 500 kbits , and my stm configurations is like this  static void MX_FDCAN1_Init(void) { /* USER CODE BEGIN FDCAN1_Init 0 */ /* USER CODE END FDCAN1_Init 0 */ FDCAN_ClkCalUnitTypeDef sCcuConfig = {0}; /* USER CODE BEGIN FDCAN1_Init 1 */ /* USER CODE END FDCAN1_Init 1 */ hfdcan1.Instance = FDCAN1; hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; hfdcan1.Init.Mode = FDCAN_MODE_NORMAL; hfdcan1.Init.AutoRetransmission = DISABLE; hfdcan1.Init.TransmitPause = DISABLE; hfdcan1.Init.ProtocolException = DISABLE; hfdcan1.Init.NominalPrescaler = 8; hfdcan1.Init.NominalSyncJumpWidth = 1; hfdcan1.Init.NominalTimeSeg1 = 13; hfdcan1.Init.NominalTimeSeg2 = 2; hfdcan1.Init.DataPres

Hi everyone,I’m currently trying to bring up an external RAM (HyperRAM over the HyperBus protocol) on the STM32L4R9I-EVAL board. While going through the documentation, I’m finding that information related to OCTOSPI and HyperBus on this family is quite scattered, and it’s been difficult to form a clear picture.From ST forums and discussions, I’ve come across mentions of a silicon/errata limitation on the STM32L4R9 family that affects HyperBus support on OCTOSPI. Some posts even suggest that PSRAM/HyperRAM is not reliably supported despite the presence of the IP, which has left me a bit confused about the actual capabilities and intended use.My goal is to use the external HyperRAM in memory-mapped mode (for example, as a framebuffer). In parallel, the board also has an external NOR flash connected over OCTOSPI (non-HyperBus), for which ST provides example projects. However, in those examples the flash is configured on OCTOSPI2, while the schematics

Hello, we have device with very old TFT display which is dying. New one is unable to obtain. It has similar interface as DCMI: vsync, hsync, pixclk, D0-D8.I have connected these clock/data lines to DCMI port, but interrupts was not triggered.Here are my clock lines (from top: vsync, hsync, pix):I suspect that timing of clock signals is not correct - compared with image I have found:

Hello,I am working on a hobby project with https://www.st.com/en/microcontrollers-microprocessors/stm32f767zi.html.I have my own build and development environment based on arm-gcc-none-eabi and CMake and all HAL Drivers and Libraries from STM.The board starts properly up and I have started to work with GPIOs. Most of my initialization routines are copied from Example Projects. I think, that they are very similar, but I´m not 100% sure yet. While initializing the LEDs, the MCU produces a HardFault (and sometimes a Memory Fault) from within the HAL Code. Currently HardFault occurs very consistently. First I want to take care about the HardFault and if MemFault is still occuring, I want to take care of this as well. The error is thrown exactly at this line:

As the subject says. I am not able to connect and re-program or debug my STM32C011 ICs after I set up SWCLK and SWDATA as ADC on my firmware.NRST pin is connected and it still doen't workI know this is expected behaviour, but I should be able to re-program it by connecting the NRST pin to the debugger, however, this is still not fixing the problem.  

Hello,Trying to do precise GPIO pulses with assembly code - on any STM Nucleo board - shows jitter and fluctuating frequency. I was told by a super user to do it via PWMI would like to add some comment that may be interesting for others :- trying to do precise pulses with PWM on the Nucleo H723 for example, still shows jitter and fluctuating frequency around the desire value. Same using HSE or HSI. Same with Nucleo-F411. Same with Nucleo-N667. I understand the reasons now.But playing around the Nucleo-N657, I got some success : if you feed your CPU_clock directly with HSE (48MHz on board), and feed the other peripherals, including timer_clock with HSE+PLL (400MHz for example), then the resulting PWM is quite accurate and stable !Regards,

Hello,I'm using the STM32H723 (at 550MHz) to generate pulses on a GPIO output at a certain frequency (around 4KHz)I'm generating the pulses with assembly code. I've stopped systick and interrupts. However, looking at the signal with a scope, I'm discovering that the frequency is not fixed, moving around the desire frequency. I've tried both with external cristal or internal HSI. Same result.What is the reason ? Is there a possibility to stabilise the output signal ?Thanks for your help,Laurent 

Hello, I want to add a SDRAM chip to my board. Processing the images with internal RAM is insuficient. Reading the manual for FMC part I'm not sure how the bandwidth is working. If I have a chip with 8/16/32 bit, is pretty clear: one chip and that's it. But if the FMC has a bandwidth set to 16 for example and I have 2 chips with bandwidth of 8 bits, FMC can access the summed capacity of these 2 chips or it will see just capacity of 1 chip? Example: 2x 512Mbit chip with 8 bit, FMC will see just capacity of 1 chip aka 512Mbit or capacity of 2 chips aka 1024Mbit if bus width is 16 bits and the chips are connected in parallel? I was thinking if the FMC bandwidth is similar like in PC where the memory controller is using 64 bit bus width to access rhw whole 4x 16bit chips capacity. Thank you.

Hello ST community,I have some troubles with dummy cycles using Quad-SPI interface in DDR mode on STM32H743 and STM32F746.I am trying to read data from IS25LP080D QSPI flash with FAST READ QUAD IO DTR MODE OPERATION (0xED command). It is 1-4-4 mode.I am having trouble with number of dummy cycles. From IS25LP080D datasheet there must be 6 dummy sclk cycles between address and data. But to get 6 dummy cycles I must set cmd.DummyCycles = 3; in my program. Why there are 3 extra dummy cycles on diagram?My read function for HAL is below. In this function I set cmd.DummyCycles = 3.IS25LP_Status_t IS25LP_ReadQuadDDR(QSPI_HandleTypeDef *hqspi, uint8_t *buf, uint32_t addr, uint32_t size) { QSPI_CommandTypeDef cmd = {0}; cmd.InstructionMode = QSPI_INSTRUCTION_1_LINE; cmd.Instruction = IS25LP_FAST_READ_QUAD_IO_DDR; cmd.AddressMode = QSPI_ADDRESS_4

One of the AF options on SPI1 is to use the SWD debug pins PB3-PB5.How can this be used in reality?Pretty obviously you can't do SWD breakpoints when SPI1 is thus mapped!But assuming no SWD debugging is needed, and you use SWD just to program the FLASH, how does one implement this? AFAICT one would need - on SWD inputs, FLASH loading will work- on SWD outputs (e.g. SWO - the SWV ITM debug output), FLASH loading works because these pins power up in some mode suitable for SWD FLASH programming.Then when the code starts running, you will need some logic to disconnect the debugger, so the clock and data SPI signals can come out, without contention with the debugger.Maybe I am missing something obvious. Or maybe this SPI1 AF mapping option is intended for FLASH programming not via SWD but via a UART, CAN or the weird USB mode.

Hi, I am using the STM32H755ZIT6 dual-core microcontroller.The internal Flash memory has a sector size of 128 KB and a page size of 4 KB. In my application, I perform erase and write operations on a specific Flash sector. If a power failure occurs while the erase or write operation is in progress, I occasionally observe that: The Flash sector being accessed becomes corrupted The sector cannot be read by the application The same sector also becomes inaccessible in STM32CubeProgrammer  This issue does not occur every time and seems to happen randomly during power loss. After full chip erasing it I can access the sector region. I would like to understand: The possible reason for this Flash corrupti

Hi everyone!Could someone help me to understand a problem with STM32G070.We have deployed approx. 50-60 devices with stm32g070 MCU that saves some parameters in FLASH every 24 hours. I know that according to datasheet FLASH memory endurance for this MCU is 1000 cycles. So, in theory, this MCU can work normally 2.7 years. It is also worth to mention that this period is defined for temperature range of -40 to +85°C. Recently, we had a relative cold weather with a temperature ranging from 0 to -10°C. This is far from -40°C that we see in datasheet. However, we had 5-6 devices that have corrupted parameters area (last page from 128K FLASH memory).I was able to reproduce this situation in the office. So I wanted to ask you guys if you had such a strange behavior with this MCU or another one. I need to mention also that this board is coated with special waterproof-coating.Erase and program functions looks like that:

Hi, I'm currently working on a project with an H755 board.The project uses UART communication. I'm developing it on a Windows 11 computer, and it generally works fine on that computer. So far, there are no issues.However, after completing the project, I'd like to be able to use it on my older laptop (currently running Windows 10 with ESU). Here's the problem: my Windows 10 computer doesn't recognize the STLink virtual COM port. It only sees the device as a standard COM port with a Microsoft driver (not ST Microelectronics), and its UART communication then doesn't work.I don't have CubeIDE installed on

1.AN5959 for STM32H523 has a note PB8/PB9 Not available for LQFP48, UFQFN48, WLCSP39.LQFP64 is not mentioned there but it has only PB8 pin and no PB9 pin. That makes it unusable by boot loader. So why it is not included in the note?My question is if the PB8 pin is still taken over by boot loader (maybe all packages use the same one)?Is there a reliable rule for partial missing IO and boot loader? What am I missing here?2. Another potential problem is that some pins for smaller packages are remapped which is noted in AN5959, but AN2606 does not always mention the alternative pin so it is dangerous to rely on that document alone. And not obvious you have to check others like AN5959 AN5711 to be sure.

Hi,Few days ago i've encountered a strange behavior of the comparator at STM32G4. I investigated the problem under controlled conditions (used Nuclo kit instead application PCB) and the result is startling.Comparator 4 configured to get positive input from pin PB0, negative from DAC1 Channel 1 (set to 500mV).Hysteresis set to maximum (70mV)DAC output is not connected to external pin (only internal connection)Input signal is 50Hz sinewave with 400mV amplitude and 600mV offset (to reliably cross 500mV thresholds +- hysteresis)Enabled Comparator 4 rising edge interrupt.Interrupt routine simply generates fixed length pulse.On blue scope trace you can see clean input signal (scope input AC coupled), it certainly does not contain noise that would be close to hysteresis value (more detail at last screen).On Red trace is application output. You can see that many times interrupt fires also on falling edge, or fires multiple times on th

Hi all,I am working on firmware that involves SPI communication using a Nucleo board (Nucleo-L4R5ZI-P) with an STM32L4ZIT6 microcontroller.I am trying to establish communication with an SPI slave device. The chip select (NSS) signal is expected to be controlled by hardware, so I enabled the hardware chip-select configuration as shown below.(screenshots attached)When I switch to software control, I am able to read from and write to the slave registers by manually toggling the chip-select pin in software. However, when I change the mode to SPI_NSS_HARD_OUTPUT, the SPI read/write communication stops working.What could be the issue? 

Hi,I am unable to flash or erase two of my STM32G030F6P6 boards. The issue started after I tried to configure the PA14 pin as GPIO_EXTI14 in CubeMX. (on two boards)After flashing the binary I was not able flash the MCU anymore. I get the error "Error in initializing ST-LINK device.".In STM32CubeProgrammer I get the error "No STM32 target found! If your product embeds Debug Authetication, please perform a discovery using Debug Authentication" when pressing "Connect" (I have no debug Authentication enabled).Then I tried enabling RST while pressing "Connect" in CubeProgrammer. I am then able to connect. But if I try to erase the flash (Full Chip Erase) I get the error "Error: Mass erase operation failed. Please verify flash protection". I have no flash protection enabled.I am on Linux using VSCode for development.Any suggestions? 

Hi, I am trying to reset HRTIM on an external event using TIM1 TRGO as a reset event. I am trying to make a single pulse every 200ms (5Hz) because I want to make a single puls test. However, I also need a high resolution so I can vary the on time and blanking time precisely, which is way I want to use the HRTIM. I have trouble getting the HRTIM to reset however, and I dont understand why. I am running the clock at 100Mhz and have set the TIM1 PSC to 9999 and ARR to 19999 to get the 5hz. I have also enabled the MSM(master/slave mode) and set the TRGO to RESET. In the HRTIM I have enabled EEV1 as source 3(TIM1_TRGO). Timer A is configured as a retriggerable single-shot mode where the reset trigger source is set so the timer counter reset is upon EEV1. The HRTIM clock is divided by 4 and the period is 50000. And I have compare unit 1 set as 49000 and compare unit 2 as 49500. The output polarity is set to active low and set and source selection is CMP1

In RM0316 rev.10, in Table 109. COMP register map and reset values, bit 1 of COMP2_CSR is marked COMP2_INP_DAC, whereas the STM32F303 are not supposed to have this bit (only STM32F301/302x6/8 do) - probably a copy/paste artefact/relict.Can ST please check/remove.JW

Hello Team, Query related to VBAT. Please refer below capture and provide your feedback for VBAT. Diode D1 and other components are, ok? Thanks & Regards,Jignesh Karena

I am currently using STM32G0B1. I found that when using an active crystal oscillator, the STM32 fails to recognize my crystal oscillator, resulting in the HSERDY bit not being set.This is the configuration of my cubemx.Use an oscilloscope to check if the crystal oscillator has started oscillating.

I'm trying to receive some data over CAN (using Kvaser CanKing 500 kbit/s) and display it on a Riverdi 12.1" display. In fdcan.c, I have: void MX_FDCAN1_Init(void) { /* USER CODE BEGIN FDCAN1_Init 0 */ FDCAN_FilterTypeDef sFilterConfig; // the required filter ID can be found in the struct /* USER CODE END FDCAN1_Init 0 */ /* USER CODE BEGIN FDCAN1_Init 1 */ /* USER CODE END FDCAN1_Init 1 */ hfdcan1.Instance = FDCAN1; hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; hfdcan1.Init.Mode = FDCAN_MODE_NORMAL; // FDCAN_MODE_INTERNAL_LOOPBACK; // FDCAN_MODE_NORMAL; hfdcan1.Init.AutoRetransmission = DISABLE; hfdcan1.Init.TransmitPause = DISABLE; hfdcan1.Init.ProtocolException = DISABLE; hfdcan1.Init

Helloi'm looking for the link to download X-CUBE-LED1642 driver but can't find itCan someone give me this link ?thanksbest regards